IDT7205L12JG IDT, Integrated Device Technology Inc, IDT7205L12JG Datasheet - Page 6

• Manufacturer Part Number: IDT7205L12JG
• Description: IC FIFO 4096X18 12NS 32PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT7205L12JG

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 40MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 7205L12JG

SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
CONTROLS:
taken to a LOW state. During reset, both internal read and write pointers are set
to the first location. A reset is required after power-up before a write operation can
take place. Both the Read Enable (R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2 (i.e. t
the rising edge of RS) and should not change until t
edge of RS.
input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-
to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM
array sequentially and independently of any on-going read operation.
the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference
between the write pointer and read pointer is less-than or equal to one-half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
of the last write signal, which inhibits further write operations. Upon the completion
of a valid read operation, the Full Flag (FF) will go HIGH after t
new valid write to begin. When the FIFO is full, the internal write pointer is blocked
from W, so external changes in W will not affect the FIFO when it is full.
Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on
a First-In/First-Out basis, independent of any ongoing write operations. After Read
Enable (R) goes HIGH, the Data Outputs (Q
impedance condition until the next Read operation. When all the data has been
read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read
cycle but inhibiting further read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after t
FIFO is empty, the internal read pointer is blocked from R so external changes will
not affect the FIFO when it is empty.
the Depth Expansion Mode, this pin is grounded to indicate that it is the first device
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
RESET ( RS ) — Reset is accomplished whenever the Reset (RS) input is
WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this
After half of the memory is filled, and at the falling edge of the next write operation,
To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge
READ ENABLE ( R ) — A read cycle is initiated on the falling edge of the Read
FIRST LOAD/RETRANSMIT ( FL/RT
0
–D
8
)
—
Data inputs for 9-bit wide data.
WEF
and a valid Read can then begin. When the
)
— This is a dual-purpose input. In
0
through Q
8
RSR
) will return to a high-
after the rising
RFF
RSS
, allowing a
before
6
loaded (see Operating Modes). The Single Device Mode is initiated by grounding
the Expansion In (XI).
when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit
operation will set the internal read pointer to the first location and will not affect the
write pointer. The status of the Flags will change depending on the relative locations
of the read and write pointers. Read Enable (R) and Write Enable (W) must be
in the HIGH state during retransmit. This feature is useful when less than 2,048/
4,096/8,192/16,384/32,768/65,536 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion Mode.
is grounded to indicate an operation in the single device mode. Expansion In (XI)
is connected to Expansion Out (XO) of the previous device in the Depth Expansion
or Daisy-Chain Mode.
OUTPUTS:
operations, when the device is full. If the read pointer is not moved after Reset (RS),
the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536
writes.
read operations, when the read pointer is equal to the write pointer, indicating that
the device is empty.
output. In the single device mode, when Expansion In (XI) is grounded, this output
acts as an indication of a half-full memory.
the Half-Full Flag (HF) will be set to LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse when the Write
pointer reaches the last location of memory, and an additional XO pulse when the
Read pointer reaches the last location of memory.
These outputs are in a high-impedance condition whenever Read (R) is in a HIGH
state.
The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data
EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI)
FULL FLAG
EMPTY FLAG ( EF ) — The Empty Flag (EF) will go LOW, inhibiting further
EXPANSION OUT/HALF-FULL FLAG ( XO/HF ) — This is a dual-purpose
After half of the memory is filled, and at the falling edge of the next write operation,
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
DATA OUTPUTS (Q
(
FF
)
— The Full Flag (FF) will go LOW, inhibiting further write
COMMERCIAL, INDUSTRIAL AND MILITARY
0
-Q
8
) — Q
0
-Q
8
are data outputs for 9-bit wide data.
TEMPERATURE RANGES
JUNE 11, 2009