IDT72605L35J IDT, Integrated Device Technology Inc, IDT72605L35J Datasheet - Page 7

• Manufacturer Part Number: IDT72605L35J
• Description: IC FIFO BI SYNC 256X18 68-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72605L35J

• Function: Synchronous
• Memory Size: 9.2K (512 x 18)
• Access Time: 35ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72605L35J

TABLE 1 ⎯ PORT A OPERATION CONTROL SIGNALS
NOTES:
1. When A
2. Regardless of the condition of A
3. If CS
of each port operate independently, Port A can be reading bypass data at the
same time Port B is reading bypass data.
A input register. Following the rising edge of CLK
Flag (FF
logic until FF
Empty Flag (EF
R/W
still controls whether Port B is in a high-impedance state. When OE
the output register data appears at D
CLK
letting Port A know that another word can be written through the bypass path.
EFB
FIFO mode (A
B output register may be overwritten. Unless Port A monitors the BYP
waits for Port B to clock out the last bypass word, data from the A→B FIFO will
overwrite data in the Port B output register. BYP
edge of CLK
B must read any bypass data in the output register on this last CLK
it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important
to monitor BYP
BYP
bypass data may also be lost.
can be handled for B→A bypass data. The Port A processor must be set up
to read the last bypass word before leaving bypass mode.
PORT A CONTROL SIGNALS
2. Port A is accessed when CS
W
EN
of CLK
from output register into three-state buffer. Refer to pin descriptions for more
information.
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
A
A
data from the Port B input register is read from the Port A output register. If A
register.
When R/W
Bypass data transfers from Port B to Port A work in a similar manner with
When the Port A address changes from bypass mode (A
Since the Port A processor controls CS
The Port A control signals pins dictate the various operations shown in Table
CS
and EN
0
0
0
0
0
0
0
1
1
B
B
A
B
are LOW, data is written into input register on the LOW-to-HIGH transition
is HIGH and EN
rising edge for this read. FFAB goes HIGH on the next CLK
and FFB
will also go HIGH after CS
A
A
A#
. If R/W
AB
2
is HIGH, then BYP
) goes LOW. Subsequent writes into Port A are blocked by internal
A
A
B
1
R/W
AB
lines determine when Data A can be written or read. If R/W
A
signifying that Port B has finished its last bypass operation. Port
2
0
A
B
0
0
0
1
1
1
1
0
1
A
A
AB
A
goes HIGH again. On the next CLKB rising edge, the A→B
= 000, the next B→A FIFO value is read out of the output register and the read pointer advances. If A
and EN
when CLK
indicating the Port A output register state.
1
A
is HIGH and OE
A
) goes HIGH indicating to Port B that data is available. Once
0
=000) on the rising edge of CLK
B
is LOW, data is read into the Port B output register. OE
EN
A
0
0
1
0
0
1
1
X
X
is LOW, data on pins D
A
B
B
is much slower than CLK
is HIGH. No bypass occur under this condition.
2
A
A
A
A
1
is LOW, and is inactive if CS
is brought HIGH; in this manner the Port B
OE
A
is LOW, data comes out of bus and is read
0
1
X
0
1
0
1
X
X
0
, the data in the Port A output register does not change and the B→A read pointer does not advance.
B0
A
-D
A
B17
and the bypass mode, this scenario
Data A
I/O
O
O
O
O
O
. EF
I
I
I
I
A
B
A0
AB
for this write, the A→B Full
will go HIGH on the rising
A
-D
Data A is written on CLK
that even though OE
a high-impedance state.
Data A is written on CLKA ≠
Data A is ignored
Data is read
Data is read
Output register does not change
Output register does not change
Data A is ignored
Data A is high-impedance
goes LOW following the
, the data held in the Port
A
A17
to avoid this condition.
is written into Port
2
A
A
A
(1)
(1)
1
is HIGH. R/
rising edge,
A
from RAM array to output register on CLK
from RAM array to output register on CLK
B
0
B
B
=001) to
(3)
is LOW,
clock or
pin and
A
A
2
and
= 0, a LOW logic level on R/W
A
1
A
A
B
(3)
0
≠. This write cycle immediately following low-impedance cycle is prohibited. Note
0 = 1XX, a flag offset register is selected and its offset is read out through Port A output
7
TABLE 2 ⎯ ACCESSING PORT A RE-
SOURCES USING CS
PROGRAMMABLE FLAGS
PAE
FF
Full offsets can be set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag Truth Table (Table
4). After reset, the programmable flag offsets are set to 8. This means the Almost-
Empty flags are asserted at Empty +8 words deep, and the Almost-Full flags are
asserted at Full -8 words deep.
and PAE
If the minimum time (t
the flag will change state on the current clock; otherwise, the flag may not change
state until the next clock rising edge. For the specific flag timings, refer to Figures
12-15.
PORT B CONTROL SIGNALS
5. Port B is independent of CS
(2)
(2)
CS
BA
, Data A is high-impedance
The IDT SyncBiFIFO has eight flags: four flags for A→B FIFO (EF
The PAE
The Port B control signal pins dictate the various operations shown in Table
, Data A is low-impedance
0
0
0
0
0
0
1
AB
). The Empty and Full flags are fixed, while the Almost-Empty and Almost-
A
, PAF
BA
is synchronized to CLK
Port A Operation
AB
AB
A
X
0
0
1
1
1
1
2
is synchronized to CLK
, FF
AB
A
, once qualified by a rising edge on CLK
SKEW2
), and four flags for B→A FIFO (EF
A
X
0
0
0
0
1
1
1
A
A
≠, Data A is high-impedance
≠, Data A is low-impedance
) between a rising CLK
2
A
1
A
A
. R/W
INDUSTRIAL TEMPERATURE RANGE
A
0
0
1
0
1
0
1
X
0
= 001, the bypass path is selected and bypass
A
, while PAE
B
B
, while PAE
and EN
A
B→A FIFO
, A
A→B FIFO Almost-Empty
B→A FIFO Almost-Empty
A→B FIFO Almost-Full
B→A FIFO Almost-Full
Read
B
BA
18-bit Bypass Path
lines determine when Data
2
AB
Port A Disabled
B
is synchronized to CLK
, A
and a rising CLK
Flag Offset
Flag Offset
Flag Offset
Flag Offset
is synchronized to CLK
1
A,
BA
will put Data A into
, AND A
A→B FIFO
, PAE
Write
BA
, PAF
A
is met,
AB
BA
0
A
B
,
,
;
.