IDT72605L35J IDT, Integrated Device Technology Inc, IDT72605L35J Datasheet - Page 8

• Manufacturer Part Number: IDT72605L35J
• Description: IC FIFO BI SYNC 256X18 68-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72605L35J

• Function: Synchronous
• Memory Size: 9.2K (512 x 18)
• Access Time: 35ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72605L35J

NOTE:
1. n = Programmable Empty Offset (PAE
NOTES:
1. When A
2. Regardless of the condition of A
TABLE 3 ⎯ FLAG OFFSET REGISTER FORMAT
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
TABLE 5 ⎯ PORT B OPERATION CONTROL SIGNALS
can be written or read in Port B. If R/W
input register, and on LOW-to-HIGH transition of CLK
register and the FIFO memory. If R/W
out of bus and is read from output register into three-state buffer. In bypass mode,
TABLE 4 ⎯ INTERNAL FLAG TRUTH TABLE
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
PAE
PAF
PAE
PAF
m = Programmable Full Offset (PAF
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
bypass data is read from the Port B output register.
R/W
From
0
0
0
1
1
1
1
D-m
AB
AB
BA
BA
n+1
Number of Words
D
0
1
B
Register
Register
Register
Register
2
A
in FIFO
1
A
0
EN
= 000 or 1XX, the next A→B FIFO value is read out of the output register and the read pointer advances. If A
0
0
1
0
0
1
1
B
D-(m+1)
D-1
To
D
0
n
OE
0
1
X
0
1
0
1
B
2
A
17
17
17
17
1
X
X
X
X
A
AB
0
, the data in the Port B output register does not change and the A→B read pointer does not advance.
AB
Data B
B
B
Register or PAF
I/O
is HIGH and OE
and EN
O
O
O
O
I
I
I
16
16
16
16
Register or PAE
X
X
X
X
HIGH
HIGH
HIGH
HIGH
LOW
EF
B
15
15
15
15
Data B is written on CLKB ↑. This write cycle immediately following output low-impedance cycle is prohibited. Note
that even though OE
impedance state.
Data B is written on CLKB ↑.
Data B is ignored
Data is read
Data is read
Output register does not change
Output register does not change
X
X
X
X
are LOW, data is written into
B
data is written into input
BA
14
14
14
14
X
X
X
X
B
BA
is LOW, data comes
Register)
(1)
(1)
Register)
from RAM array to output register on CLKB ≠ Data B is low-impedance
from RAM array to output register on CLKB ≠, Data B is high- impedance
13
13
13
13
X
X
X
X
B
= 0, a LOW logic level on R/W
12
12
12
12
X
X
X
X
11
11
11
11
HIGH
HIGH
HIGH
X
X
X
X
PAE
LOW
LOW
(2)
(2)
8
, Data B is high-impedance
, Data B is low-impedance
if R/W
If R/W
Refer to pin descriptions for more information.
10
10
10
10
X
X
X
X
B
A
is LOW, bypass messages are transferred into B→A output register.
Port B Operation
is HIGH, bypass messages are transferred into A→B output register.
X
X
X
X
9
9
9
9
B
, once qualified by a rising edge on CLK
8
8
8
8
7
7
7
7
HIGH
HIGH
HIGH
LOW
LOW
A→B FIFO Almost-Empty Flag Offset
B→A FIFO Almost-Empty Flag Offset
PAF
A→B FIFO Almost-Full Flag Offset
B→A FIFO Almost-Full Flag Offset
6
6
6
6
INDUSTRIAL TEMPERATURE RANGE
2
A
1
A
5
5
5
5
0
= 001, the bypass path is selected and
4
4
4
4
B,
3
3
3
3
will put Data B into a high-
HIGH
HIGH
HIGH
HIGH
LOW
2
2
2
2
FF
1
1
1
1
0
0
0
0