AD8016ARP-EVAL Analog Devices, AD8016ARP-EVAL Datasheet - Page 11

• Manufacturer Part Number: AD8016ARP-EVAL
• Description: Low Power, High Output Current xDSL Line Driver
• Manufacturer: Analog Devices

THEORY OF OPERATION
The AD8016 is a current feedback amplifier with high (500 mA)
output current capability. With a current feedback amplifier the
current into the inverting input is the feedback signal and the
open-loop behavior is that of a transimpedance, dVo/dIin or T
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 37 shows a
simplified model of a current feedback amplifier. Since R
proportional to 1/g
where g
analysis of the follower with gain circuit yields:
where:
Recognizing that G × R
result of constant bandwidth with gain for current feedback
amplifiers is evident, the 3 dB point being set when |T
Of course, for a real amplifier there are additional poles that
contribute excess phase and there will be a value for R
which the amplifier is unstable. Tolerance for peaking and desired
flatness will determine the optimum R
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power saving.
The AD8016 is also unique in that it has a power management
system included on-chip. It features four user programmable
power levels (all of which provide a low output impedance of the
driver), as well as the provision for complete shutdown (high
impedance state). Also featured is a thermal shutdown with
alarm signal.
POWER SUPPLY AND DECOUPLING
The AD8016 should be powered with a good quality (i.e., low
noise) dual supply of ± 12 V for the best distortion and Multi-
tone Power Ratio (MTPR) performance. Careful attention must
be paid to decoupling the power supply pins. A 10 µF capacitor
located in near proximity to the AD8016 is required to provide
good decoupling for lower frequency signals. In addition, 0.1 µF
decoupling capacitors should be located as close to each of the
four power supply pins as is physically possible. All ground pins
should be connected to a common low impedance ground
plane.
m
is the transconductance of the input stage. Basic
V
IN
V
V
IN
R
O
G
R
m
=
N
, the equivalent voltage gain is just T
G
R
IN
–
+
×
IN
G
<< R
T S
=
I
R
Z
IN
=
IN
( )
g
1
1
F
m
+
T
+
for low gains, the familiar
Z
+
R
≈
F
R
R
T S
G
25 Ω
G
Z
F
F
( )
×
in each application.
R
IN
+
R
F
V
OUT
F
Z
| = R
below
Z
IN
× g
is
F
m
Z
.
,
.
FEEDBACK RESISTOR SELECTION
In current feedback amplifiers, selection of feedback and gain
resistors will have an impact on the MTPR performance, band-
width and gain flatness. Care should be exercised in the selec-
tion of these resistors so that optimum performance is achieved.
The table below shows the recommended resistor values for use
in a variety of gain settings. These values are suggested as a
good starting point when designing for any application.
BIAS PIN AND PWDN FEATURES
The AD8016 is designed to cover both CO (Central Office) and
CPE (Customer Premise Equipment) ends of an xDSL applica-
tion. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
steps) to full OFF (via BIAS pin). This versatility gives the
modem designer the flexibility to maximize efficiency while
maintaining reasonable levels of Multitone Power Ratio (MTPR)
performance. Optimizing driver efficiency while delivering the
required DMT power is accomplished with the AD8016 through
the use of on-chip power management features. Two digitally
programmable logic pins, PWDN1 and PWDN0, may be used
to select four different bias levels; 100%, 60%, 40%, and 25%
of full quiescent power (see Table II).
PWDN1
Code
1
1
0
0
X
The bias level can be controlled with TTL logic levels (HI = 1)
applied to PWDN1 and PWDN0 pins alone or in combination
with BIAS control pin. The DGND or digital ground pin is the
logic ground reference for PWDN1 and PWDN0 pins. In typical
ADSL applications where ± 12 V or ± 6 V supplies (also single
supplies) are used, the DGND pin is connected to analog ground.
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and thus quiescent current I
pulling out a current of 0 µA (or open) to approximately 200 µA,
the quiescent current can be adjusted from 100% (full ON) to a
full OFF condition. The full OFF condition yields a high output
impedance. Because of on-chip resistor variation of up to ± 20%
the actual amount of current required to fully shut down the
AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250 µA is recommended. See Figure 38 for
logic drive circuit for complete amplifier shutdown. Figures 34
and 35 show the relationship between current pulled out of
Gain
+1
–1
+2
+5
+10
Table II. PWDN Code Selection Guide
Table I. Resistor Selection Guide
PWDN0
Code
1
0
1
0
X
R
1 k
500
650
750
1 k
F
( )
Quiescent Bias Level
100% (Full ON)
60%
40%
25% (Low Z
Full OFF (High Z
Pulled Out of BIAS Pin)
OUT
R
∞
500
650
187
111
AD8016
G
but Not OFF)
( )
OUT
via 250 µA
Q
. By