AD8364-EVAL-500 Analog Devices, AD8364-EVAL-500 Datasheet - Page 19

• Manufacturer Part Number: AD8364-EVAL-500
• Description: LF to 2.7GHz, Dual 60dB TruPwr™ Detector; Package: EVALUATION BOARDS; No of Pins: -; Temperature Range: Commercial
• Manufacturer: Analog Devices

SQUARE LAW DETECTOR AND AMPLITUDE TARGET
The output of the VGA, called V
square law detector. The detector provides the true rms
response of the RF input signal, independent of waveform, up
to a crest factor of 6. The detector output, called I
fluctuating current with positive mean value. The difference
between I
integrated by C
the on-chip 25 pF filter capacitor. CLP[A, B] can be used to
arbitrarily increase the averaging time while trading off
response time. When the AGC loop is at equilibrium,
This equilibrium occurs only when
where V
Because the square law detectors are electrically identical and
well matched, process and temperature dependant variations
are effectively cancelled.
By forcing the above identity through varying the VGA
setpoint, it is apparent that
Substituting the value of V
When connected as a measurement device VST[A, B] =
OUT[A, B]. Solving for OUT[A, B] as a function of RF
where V
100 MHz. V
RMS(RF
altered by using a resistor divider from OUT[A, B] to drive
VST[A, B]. The intercept, V
(−62 dBm, referred to 50 Ω) with a CW signal at 100 MHz. This
value is extrapolated, because OUT[A, B] do not respond to input
of less than approximately −55 dBm with differential drive.
In most applications, the AGC loop is closed through the
setpoint interface, VST[A, B]. In measurement mode, OUT[A, B]
are tied to VST[A, B], respectively. In controller mode, a control
voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control
input of a system. The RF feedback signal to the input pins is
forced to have an rms value determined by VSTA or VSTB.
MEAN(I
MEAN(V
RMS(V
RMS(G0 × RF
OUT[A, B] = V
TGT
SLOPE
IN
SQU
) = V
is an attenuated version of the VREF voltage.
SIG
Z
is laser trimmed to 1 V/decade (or 50 mV/dB) at
and an internally generated current, I
SQU
is the intercept voltage, since Log 10(1) = 0 when
SIG
) = √(MEAN(V
Z
F
. If desired, the effective value of V
) = I
2
and a capacitor attached to CLP[A, B]. CF is
) = V
IN
SLOPE
TGT[A, B]
exp(−VST[A, B]/V
TGT[A, B]
× Log10(RMS(RF
SIG
Z
2
, we have
, is also laser trimmed to 180 µV
SIG
2
)) = √(V
SIG
, is applied to a wideband
GNS
TGT
)) = V
IN
2
)/V
) = V
Z
)
TGT
SQU
TGT
TGT[A, B]
SLOPE
, is a
IN
may be
,
, is
(3)
(4)
(5)
(6)
(7)
Rev. 0 | Page 19 of 48
RF INPUT INTERFACE
The AD8364’s RF inputs are connected as shown in Figure 52.
There are 100 Ω resistors connected between DEC[A, B] and
INH[A, B] and also between DEC[A, B] and INL[A, B]. The
DEC[A, B] pins have a dc level established as (7 × VPS[A, B] +
55 × V
2.5 V.
Signal-coupling capacitors must be connected from the input
signal to the INH[A, B] and INL[A, B] pins. The high-pass
corner is
A decoupling capacitor should be connected from DEC[A, B] to
ground to attenuate any signal at the midpoint. A 100 pF and
0.1 µF cap from DEC[A, B] to ground are recommended, with a
1 nF coupling capacitor such that signals greater than 1.6 MHz
can be measured. For coupling signals less than 1.6 MHz,
100 × C
OFFSET COMPENSATION
An offset-nulling loop is used to address small dc offsets in the
VGA. The high-pass corner frequency of this loop is internally
preset to about 1 MHz using an on-chip capacitor of 25 pF
(1/(2 × 5K × 25 pF)), which is sufficiently low for most HF
applications. The high-pass corner can be reduced by a
capacitor from CHP[A, B] to ground. The input offset voltage
varies depending on the actual gain at which the VGA is
operating and, thus, on the input signal amplitude. When an
excessively large value of CHP[A, B] is used, the offset
correction process may lag the more rapid changes in the VGA’s
gain, which may increase the time required for the loop to fully
settle for a given steady input amplitude.
f
high-pass
BE
coupling
)/30. With a 5 V supply, DEC[A, B] is approximately
= 1/(2 × π × 100 × C)
DEC[A, B]
INH[A, B]
INL[A, B]
for the DEC[A, B] capacitor generally can be used.
Figure 52. AD8364 RF Inputs
VSP[A, B]
COM[A, B]
V
IN
100Ω
100Ω
COM[A, B]
COM[A, B]
VSP[A, B]
VGA
VSP[A, B]
AD8364
(8)