SN74LS259D Motorola, SN74LS259D Datasheet - Page 2

• Manufacturer Part Number: SN74LS259D
• Description: 8-BIT ADDRESSABLE LATCH
• Manufacturer: Motorola

FUNCTIONAL DESCRIPTION
in the mode selection table. In the addressable latch mode,
data on the Data line (D) is written into the addressed
latch.The addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
LOGIC DIAGRAM
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
Q N–1 = Previous Output State
H
E
H
L
L
The SN54 / 74LS259 has four modes of operation as shown
In the one-of-eight decoding or demultiplexing mode, the
H
H
C
L
L
MODE SELECTION
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
Q 0
4
14
E
MODE
D
13
Q 1
5
1
A 0
C E D A 0
H H X
H I
H L H
H L L
H L H
H L L
H L H
L H X
L L L
L L H
L L L
L L H
L L H
Q 2
6
I
2
A 1
X
H
H
H
X
H
H
H
H
L
L
L
L
FAST AND LS TTL DATA
SN54/74LS259
A 2
A 1
Q 3
H
H
H
X
L
L
L
L
X
L
L
L
L
3
7
A 2
X
H
X
H
H
L
L
L
L
L
L
L
L
5-434
Q N–1
Q N–1
Q N–1
Q N–1
Q N–1
Q 0
H
H
L
L
L
L
L
L
Q 4
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs are
LOW and unaffected by the address and data inputs.
latch, changing more then one bit of the address could impose
a transient wrong address. Therefore, this should only be
done while in the memory mode.
15
PRESENT OUTPUT STATES
9
When operating the SN54 / 74LS259 as an addressable
The truth table below summarizes the operations.
Q N–1
Q N–1
C
Q 1
H
H
L
L
L
L
L
L
TRUTH TABLE
Q N–1
Q N–1
Q N–1
Q N–1
Q 2
L
L
L
L
L
L
Q 5
10
Q N–1
Q 3
L
L
L
L
L
L
Q 4
L
L
L
L
L
L
Q 6
11
Q 5
L
L
L
L
L
L
V CC = PIN 16
GND = PIN 8
= PIN NUMBERS
Q N–1
Q N–1
Q 6
L
L
L
L
L
L
Q 7
12
Q 7
H
H
L
L
L
L
L
L
Clear
Demultiplex
Memory
Addressable
Latch
MODE