LM3S1512 Luminary Micro, Inc, LM3S1512 Datasheet - Page 106

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LM3S1512

Manufacturer Part Number
LM3S1512
Description
Lm3s1512 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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System Control
106
Bit/Field
5
4
3
2
1
0
reserved
UART2
UART1
UART0
Name
SSI1
SSI0
Type
R/W
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
0
Preliminary
Description
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
July 25, 2008

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