LM3S1512 Luminary Micro, Inc, LM3S1512 Datasheet - Page 467

• Manufacturer Part Number: LM3S1512
• Description: Lm3s1512 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 25, 2008
QEI
SSI
System Control &
Clocks
Function
VBAT
VDD25
VDD25
VDD25
VDD25
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDDA
VDDA
WAKE
IDX0
PhA0
PhB0
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
SSI1Clk
SSI1Fss
SSI1Rx
SSI1Tx
CMOD0
Pin Name
Number
G12
H10
G10
M10
L12
E10
G11
A11
B12
B11
A12
E11
Pin
M9
M4
M5
C3
D3
G3
K7
K8
K9
C6
C7
G1
G2
F3
L4
L5
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
Buffer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
An external input that brings the processor out of
hibernate mode when asserted.
QEI module 0 index
QEI module 0 Phase A
QEI module 1 Phase B
SSI module 0 clock
SSI module 0 frame
SSI module 0 receive
SSI module 0 transmit
SSI module 1 clock
SSI module 1 frame
SSI module 1 receive
SSI module 1 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
LM3S1512 Microcontroller
Description
467