LM3S1601 Luminary Micro, Inc, LM3S1601 Datasheet - Page 162

• Manufacturer Part Number: LM3S1601
• Description: Lm3s1601 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Input/Outputs (GPIOs)
9.1.2
162
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-2 on page 162, where u is data unchanged by the write.
Figure 9-2. GPIODATA Write Example
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 162.
Figure 9-3. GPIODATA Read Example
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■
■
■
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 172).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 173 and page 174). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Returned Value
GPIO Interrupt Sense (GPIOIS) register (see page 169)
GPIO Interrupt Both Edges (GPIOIBE) register (see page 170)
GPIO Interrupt Event (GPIOIEV) register (see page 171)
GPIODATA
GPIODATA
ADDR[9:2]
ADDR[9:2]
0x0C4
0x098
0xEB
0
1
u
0
1
0
9
7
9
7
8
0
1
u
6
8
0
0
0
6
7
1
1
1
5
7
1
1
1
5
6
0
0
u
4
6
1
1
1
4
5
0
1
u
3
5
0
1
0
3
4
1
0
0
2
4
0
1
0
2
3
1
1
1
1
3
0
1
0
1
Preliminary
2
0
1
u
0
2
1
0
0
0
1
1
1
0
0
0
0
0
July 26, 2008