LM3S1601 Luminary Micro, Inc, LM3S1601 Datasheet - Page 324

• Manufacturer Part Number: LM3S1601
• Description: Lm3s1601 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Synchronous Serial Interface (SSI)
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
324
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
RO
RO
30
14
0
0
reserved
RORMIS
RO
RO
29
13
RXMIS
TXMIS
RTMIS
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TXMIS
RO
RO
19
0
3
0
RXMIS
RO
RO
18
0
2
0
July 26, 2008
RTMIS
RO
RO
17
0
1
0
RORMIS
RO
RO
16
0
0
0