LM3S1918 Luminary Micro, Inc, LM3S1918 Datasheet - Page 60

• Manufacturer Part Number: LM3S1918
• Description: Lm3s1918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.1.2.6
6.1.2.7
60
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper V
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 20-12 on page 463.
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 64). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1.
2.
3.
The software-initiated system reset timing is shown in Figure 20-13 on page 463.
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1.
2.
3.
A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
An internal reset is asserted.
The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The watchdog timer times out for the second time without being serviced.
An internal reset is asserted.
The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
DD
level is restored. The RESC register can be examined in the reset interrupt
Preliminary
July 26, 2008