LM3S2608 Luminary Micro, Inc, LM3S2608 Datasheet - Page 88

• Manufacturer Part Number: LM3S2608
• Description: Lm3s2608 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
System Control
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0101.32FF
88
Bit/Field
31:25
23:17
15:12
11:10
24
16
RO
RO
31
15
0
0
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
RO
RO
30
14
0
MINSYSDIV
0
MINSYSDIV
reserved
reserved
reserved
RO
RO
29
13
0
1
Name
CAN0
ADC
reserved
RO
RO
28
12
0
1
RO
RO
27
11
0
0
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
Reset
0x3
RO
RO
MAXADCSPD
25
0
9
1
0
1
0
1
0
Preliminary
CAN0
RO
RO
24
1
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module Present
When set, indicates that the ADC module is present.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Value
0x3
MPU
RO
RO
23
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0
7
1
HIB
RO
RO
22
0
6
1
TEMPSNS
RO
RO
21
0
5
1
reserved
PLL
RO
RO
20
0
4
1
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
July 26, 2008
SWD
RO
RO
17
0
1
1
JTAG
ADC
RO
RO
16
1
0
1