LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 269

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

13.2.4.6
July 5, 2006
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
In this configuration, during idle periods:
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be
immediately transferred onto the SSIRx line of the master. The master SSITx output pad is
enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be
pulsed High between each data word transfer. This is because the slave select pin freezes the
data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero.
Therefore, the master device must raise the SSIFss pin of the slave device between each data
transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured.
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in
Figure 13-9, which covers both single and continuous transfers.
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1
Note:
SSIClk
SSIFss
SSIClk is forced High
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
SSIRx
SSITx
SSITx/SSIRx
Q is undefined in Figure 13-9.
SSIClk
SSIFss
Q
LSB
MSB
MSB
MSB
Preliminary
4 to 16 bits
4 to 16 bits
LSB
LM3S301 Data Sheet
LSB
LSB
MSB
Q
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