LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 46

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

JTAG Interface
5.4
5.4.1
Table 5-2. JTAG Instruction Register Commands
5.4.1.1
5.4.1.2
46
All Others
IR[3:0]
0000
0001
0010
1000
1010
1011
1110
1111
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The
registers can be broken down into two main categories: Instruction Registers and Data Registers.
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2. A detailed explanation of each instruction, along with its
associated Data Register, follows.
EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction
Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and
output enables are used to drive the GPIO pads rather than the signals coming from the core. This
allows tests to be developed that drive known values out of the controller, which can be used to
verify connectivity.
INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/
PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the
preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows
SAMPLE / PRELOAD
Instruction
Reserved
EXTEST
IDCODE
BYPASS
INTEST
ABORT
DPACC
APACC
Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
Shifts data into the ARM Debug Port Abort Register.
Shifts data into and out of the ARM DP Access Register.
Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
Connects TDI to TDO through a single Shift Register chain.
Defaults to the BYPASS instruction to ensure that TDI is always
connected to TDO.
Preliminary
July 5, 2006