LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 276

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
276
Reset
Reset
Type
Type
SSI Control 1 (SSCR1)
Offset 0x004
Bit/Field
RO
RO
31
15
0
0
31:4
3
2
1
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
RO
RO
30
14
0
0
reserved
Name
SOD
SSE
MS
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
R/W
R/W
R/W
27
11
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
0
0
0
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In
multiple-slave systems, it is possible for the SSI master to
broadcast a message to all slaves in the system while
ensuring that only one slave drives data onto the serial output
line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD
bit can be configured so that the SSI slave does not drive the
SSITx pin.
0: SSI can drive SSITx output in Slave Output mode.
1: SSI must not drive the SSITx output in Slave mode.
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified
only when SSI is disabled (SSE=0).
0: Device configured as a master.
1: Device configured as a slave.
Setting this bit enables SSI operation.
0: SSI operation disabled.
1: SSI operation enabled.
Note:
SSI Synchronous Serial Port Enable
reserved
RO
RO
23
0
7
0
This bit must be set to 0 before any control registers
are reprogrammed.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
SOD
R/W
RO
19
0
3
0
MS
R/W
RO
18
0
2
0
SSE
R/W
RO
17
0
1
0
July 5, 2006
LBM
R/W
RO
16
0
0
0