IDT72V36100L10PF IDT, Integrated Device Technology Inc, IDT72V36100L10PF Datasheet - Page 16

• Manufacturer Part Number: IDT72V36100L10PF
• Description: IC FIFO 64X36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36100L10PF

• Function: Synchronous
• Memory Size: 2.3K (64 x 36)
• Data Rate: 166MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36100L10PF

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
D/Q17
D/Q35
D/Q35
1st Parallel Offset Write/Read Cycle
D/Q17
2nd Parallel Offset Write/Read Cycle
D/Q16
16
D/Q16
IDT72V36100 ⎯
16
16
15
16
15
IDT72V36100/IDT72V36110 ⎯ x36 Bus Width
14
15
D/Q19
D/Q19
EMPTY OFFSET (LSB) REGISTER (PAE)
14
15
14
13
FULL OFFSET (LSB) REGISTER (PAF)
17
17
14
13
D/Q17
13
D/Q17
12
13
12
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
11
12
17
17
16
16
Data Inputs/Outputs
11
12
EMPTY OFFSET REGISTER (PAE)
11
10
16
15
16
FULL OFFSET REGISTER (PAF)
15
11
10
10
14
15
9
15
14
10
D/Q8
x18 Bus Width
9
14
13
14
13
9
D/Q8
9
13
12
13
12
8
8
8
8
12
11
11
7
12
7
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
7
7
11
10
6
6
11
10
# of Bits Used
6
6
10
5
5
10
9
9
D/Q8
5
5
D/Q8
4
4
9
9
4
4
3
3
8
8
8
8
3
3
2
2
7
7
7
7
# of Bits Used
# of Bits Used
D/Q0
2
2
1
1
6
6
6
6
D/Q0
1
1
5
5
5
5
Interspersed
Parity
Non-Interspersed
Parity
4
4
4
4
3
3
3
3
TM
2
2
2
2
36-BIT FIFO
D/Q0
D/Q0
1
1
1
1
Non-Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
Interspersed
Parity
16
D/Q17
D/Q17 D/Q16
D/Q17
D/Q17 D/Q16
1st Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q16
D/Q16
16
16
16
15
15
16
14
14
15
15
EMPTY OFFSET (LSB) REGISTER (PAE)
FULL OFFSET (LSB) REGISTER (PAF)
FULL OFFSET (MSB) REGISTER (PAF)
EMPTY OFFSET (MSB) REGISTER (PAE)
14
14
13
13
13
12
IDT72V36110 ⎯
13
12
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
11
11
12
12
11
10
11
10
10
10
9
9
D/Q8
D/Q8
9
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
9
8
8
8
8
7
7
7
7
6
6
COMMERCIAL AND INDUSTRIAL
6
6
x18 Bus Width
# of Bits Used
5
5
5
5
4
4
4
4
3
3
TEMPERATURE RANGES
3
3
2
2
2
2
OCTOBER 22, 2008
D/Q0
D/Q0
D/Q0
D/Q0
17
17
17
17
1
1
1
1
Interspersed
Parity
Non-Interspersed
Parity
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