AD5532-1 Analog Devices, AD5532-1 Datasheet - Page 13

• Manufacturer Part Number: AD5532-1
• Description: 32-Channel/ 14-Bit Voltage-Output DAC
• Manufacturer: Analog Devices

DB13–DB0
These are used to write a 14-bit word into the addressed DAC
register. Clearly, this is only valid when in DAC mode.
The serial interface is designed to allow easy interfacing to
most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI,
SPI, DSP56000, TMS320, and ADSP-21xx, without the need
for any glue logic. When interfacing to the 8051, the SCLK
must be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.
Figures 3, 4, and 5 show the timing diagram for a serial read and
write to the AD5532. The serial interface works with both a con-
tinuous and a noncontinuous serial clock. The first falling edge of
SYNC resets a counter that counts the number of serial clocks to
ensure the correct number of bits are shifted in and out of the
serial shift registers. Any further edges on SYNC are ignored until
the correct number of bits are shifted in or out. Once the correct
number of bits for the selected mode have been shifted in or out,
the SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of SYNC.
In readback, the first rising SCLK edge after the falling edge of
SYNC causes D
is clocked out onto the D
rising edges. The D
state on the falling edge of the fourteenth SCLK. Data on the
D
IN
line is latched in on the first SCLK falling edge after the
OUT
OUT
to leave its high impedance state and data
MSB
MSB
MSB
pin goes back into a high impedance
OUT
1
1
MODE BITS
MODE BITS
line and also on subsequent SCLK
0
MODE BITS
MSB
MODE BIT 1
1
0
0
1
MODE BITS
WRITTEN TO PART
WRITTEN TO PART
SERIAL WORD
SERIAL WORD
MODE BIT 2
CAL
CAL
10-BIT
10-BIT
CAL
0
OFFSET SEL
OFFSET SEL
OFFSET SEL
CAL
TEST BIT
TEST BIT
OFFSET SEL
0
falling edge of the SYNC signal and on subsequent SCLK fall-
ing edges. During readback D
will not shift data in or out until it receives the falling edge of
the SYNC signal.
Parallel Interface (SHA Mode Only)
The SER/PAR bit must be tied low to enable the parallel inter-
face and disable the serial interface. The parallel interface is
controlled by 9 pins.
CS
Active low package select pin. This pin is shared with the SYNC
function for the serial interface.
WR
Active low write pin. The values on the address pins are latched
on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed. The address on A4–A0 is ignored in this case.
Cal
When this pin is high, all 32 channels acquire V
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.
0
TEST BIT
0
A4 –A0
A4 –A0
A4 –A0
LSB
LSB
TEST BIT
0
NEXT FALLING EDGE OF SYNC
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
(DB13 = MSB OF DAC WORD)
READ FROM PART AFTER
READ FROM PART AFTER
MSB
A4 –A0
MSB
14-BIT DATA
DB1 3 –DB0
14-BIT DATA
DB1 3 –DB0
DB1 3 –DB0
LSB
IN
is ignored. The serial interface
LSB
LSB
LSB
IN
AD5532
simultaneously.