LTC2241-12 Linear Technology, LTC2241-12 Datasheet
LTC2241-12
Related parts for LTC2241-12
LTC2241-12 Summary of contents
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... ENCODE INPUT DESCRIPTIO The LTC converter designed for digitizing high frequency, wide dynamic range signals. The LTC2241-12 is perfect for demanding communications applications with AC perfor- mance that includes 65.5dB SNR and 78dB SFDR. Ultralow jitter of 95fs noise performance. DC specs include ±0.7LSB INL (typ), ±0.4LSB DNL (typ) and no missing codes over temperature ...
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... LTC2241- ABSOLUTE AXI U RATI GS Supply Voltage (V ) .............................................. 2.8V DD Digital Output Ground Voltage (OGND) ....... –0. Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ............... –0. FIGURATIO ...
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... Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input f = 135MHz 140MHz IN1 IN2 LTC2241-12 MIN TYP MAX UNITS ● 12 Bits ±0.7 ● –2.3 2.3 LSB ±0.4 ● –1 1 LSB ± ...
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... LTC2241- TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM www.datasheet4u.com V Line Regulation CM V Output Resistance DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) V Differential Input Voltage ...
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... Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (t – (Note (Note 7) (Note 7) (t – (Note LTC2241-12 MIN TYP MAX UNITS ● 2.375 2.5 2.625 ● 2.375 2.5 2.625 V ● ...
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... LTC2241-12 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device www.datasheet4u.com reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted) ...
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... RANGE RANGE 45 40 100 200 600 700 1000 0 300 400 500 INPUT FREQUENCY (MHz) LTC2241- 25°C unless otherwise noted, Note 4) A 8192 Point FFT –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 – ...
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... LTC2241-12 W TYPICAL PERFOR A CE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range 30MHz, –1dB, IN www.datasheet4u.com LVDS Mode 95 90 SFDR SNR 100 150 200 SAMPLE RATE (Msps) 224112 G13 I vs Sample Rate, 5MHz Sine VDD Wave Input, –1dB ...
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... Output and Input Common Mode CM Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. LTC2241-12 selects demux CMOS mode with simulta- DD selects demux DD selects offset DD selects 2’ ...
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... LTC2241- CTIO S (LVDS Mode) + AIN (Pins 1, 2): Positive Differential Analog Input. www.datasheet4u.com – AIN (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor ...
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... CLOCK DRIVER REFLB REFHA REFLA REFHB 2.2µF + – ENC ENC 0.1µF 0.1µF 1µF 1µF Figure 1. Functional Block Diagram LTC2241-12 FOURTH PIPELINED FIFTH PIPELINED ADC STAGE ADC STAGE SHIFT REGISTER AND CORRECTION CONTROL OUTPUT LOGIC DRIVERS 224112 F01 OGND LVDS SHDN M0DE ...
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... LTC2241- DIAGRA S www.datasheet4u.com ANALOG INPUT – ENC + ENC D0-D11, OF – CLKOUT + CLKOUT ANALOG INPUT – ENC + ENC DA0-DA11, OFA CLKOUTB CLKOUTA DB0-DB11, OFB 12 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels ...
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... All Outputs Are Single-Ended and Have CMOS Levels – – LTC2241- – – – 2 224112 TD03 – – – – 1 224112 TD04 224112fa 13 ...
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... AC input. The signal to noise ratio due to the jitter alone will be: SNR CONVERTER OPERATION As shown in Figure 1, the LTC2241- CMOS pipelined multi-step converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2241-12 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C NMOS transistors. The capacitors shown attached to each ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2241-12 being driven transformer with a center tapped secondary. The second- ary center tap is DC biased with V signal at its optimum DC level. Terminating on the trans- ...
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... ADC bandwidth. Reference Operation Figure 9 shows the LTC2241-12 reference circuitry con- sisting of a 1.25V bandgap reference, a difference ampli- fier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (± ...
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... See the Typical Performance Character- BUFFER istics section. INTERNAL ADC HIGH REFERENCE Driving the Encode Inputs The noise performance of the LTC2241-12 can depend DIFF AMP on the encode signal quality as much as on the analog input. The ENC differentially, primarily for noise immunity from com- INTERNAL ADC mon mode noise sources ...
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... To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V resistors. The lower limit of the LTC2241-12 sample rate is deter- mined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors ...
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... As with all high speed/high resolution converters, the digi- tal output loading can affect the performance. The digital outputs of the LTC2241-12 should drive a minimal capaci- tive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch ...
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... LOGIC LATCH OE Figure 13a. Digital Output Buffer in CMOS Mode Data Format The LTC2241-12 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V selects offset binary output format. Connecting ...
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... The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2241-12 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good and ...
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... PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. LTC2241-12 224112fa 23 ...
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... LTC2241- APPLICATIO S I FOR ATIO www.datasheet4u.com 224112fa ...
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... U U APPLICATIO S I FOR ATIO Silkscreen Top www.datasheet4u.com Layer 1 Component Side W U LTC2241-12 Layer 2 GND Plane Layer 3 Power/Ground Plane 25 224112fa ...
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... LTC2241- APPLICATIO S I FOR ATIO Layer 4 Power/Ground Planes www.datasheet4u.com Layer 5 Power/Ground Planes Layer Back Solder Side Silk Screen Back, Solder Side 224112fa ...
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... PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0.05 7.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2241-12 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4 ...
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... LTC2241-12 RELATED PARTS PART NUMBER DESCRIPTION LTC1748 14-Bit, 80Msps, 5V ADC www.datasheet4u.com LTC1750 14-Bit, 80Msps, 5V Wideband ADC ® LT 1993-2 High Speed Differential Op Amp LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs LTC2220 12-Bit, 170Msps, 3 ...