LTC2241-12 Linear Technology, LTC2241-12 Datasheet - Page 21

• Manufacturer Part Number: LTC2241-12
• Description: 210Msps ADC
• Manufacturer: Linear Technology

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Data Format
The LTC2241-12 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
0
1/3V
2/3V
V
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
APPLICATIO S I FOR ATIO
LTC2241-12
DD
LATCH
FROM
DATA
OE
DD
DD
DD
DD
Figure 13a. Digital Output Buffer in CMOS Mode
PREDRIVER
selects offset binary output format. Connecting
or 2/3V
LOGIC
V
DD
DD
OUTPUT FORMAT
2’s Complement
2’s Complement
DD
Offset Binary
Offset Binary
or V
logic values. Table 3 shows the logic
U
DD
selects 2’s complement output
U
V
DD
+
/OF
W
CYCLE STABILIZER
OV
DD
–
CLOCK DUTY
pins indicates an
+
43Ω
Off
On
On
Off
2241 F13a
input available
OV
OGND
U
DD
TYPICAL
DATA
OUTPUT
0.1µF
0.5V
TO 2.625V
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT
edge of CLKOUT
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV
In the CMOS output mode, OV
voltage up to 2.625V. OGND can be powered with any volt-
age from GND up to 1V and must be less than OV
logic outputs will swing between OGND and OV
In the LVDS output mode, OV
2.5V supply and OGND should be connected to GND.
LTC2241-12
+
/CLKOUT
–
+
Figure 13b. Digital Output in LVDS Mode
D
D
1.25V
DD
+
/CLKOUT
should be tied to that same 1.8V supply.
–
10k
rises and can be latched on the falling
10k
3.5mA
–
.
DD
DD
should be connected to a
can be powered with any
224112 F13b
D
D
LTC2241-12
OUT
OUT
100Ω
DD
+
–
OGND
OV
, should be tied
DD
0.1µF
RECEIVER
DD
LVDS
21
DD
.
224112fa
2.5V
. The