LTC2241-12 Linear Technology, LTC2241-12 Datasheet - Page 20

• Manufacturer Part Number: LTC2241-12
• Description: 210Msps ADC
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
Table 1. Output Codes vs Input Voltage
LTC2241-12
Digital Output Modes
The LTC2241-12 can operate in several digital output
modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3V
resistor divider can be used to set the 1/3V
logic values. Table 2 shows the logic states for the LVDS
pin.
Table 2. LVDS Pin Function
LVDS
GND
1/3V
2/3V
V
20
>+1.000000V
<–1.000000V
DD
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
0.000000V
(2V RANGE)
DD
DD
A
IN
+
– A
IN
–
DIGITAL OUTPUT MODE
Full-Rate CMOS
Demultiplexed CMOS, Simultaneous Update
Demultiplexed CMOS, Interleaved Update
LVDS
OF
1
0
0
0
0
0
0
0
0
1
U
(OFFSET BINARY)
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
DD
U
D11 – D0
, 2/3V
DD
W
or V
(2’s COMPLEMENT)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
DD
DD
. An external
D11 – D0
U
or 2/3V
DD
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single
output buffer in the CMOS output mode. Each buffer is
powered by OV
ADC power and ground. The additional N-channel transis-
tor in the output driver allows operation down to voltages
as low as 0.5V. The internal resistor in series with the
output makes the output appear as 50Ω to external cir-
cuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the digi-
tal output loading can affect the performance. The digital
outputs of the LTC2241-12 should drive a minimal capaci-
tive load to avoid possible interaction between the digital
outputs and sensitive input circuitry. The output should be
buffered with a device such as an 74VCX245 CMOS latch.
For full speed operation the capacitive load should be kept
under 10pF.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
+
/OF
–
or CLKOUT
DD
voltages will also help reduce interference
DD
+
and OGND, which are isolated from the
to OUT
+
/CLKOUT
–
or vice versa which creates a
–
). To minimize noise the
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