S29AL004D SPANSION, S29AL004D Datasheet - Page 23

• Manufacturer Part Number: S29AL004D
• Description: 4 Megabit (512 Kx 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: SPANSION

Note:
February 18, 2005 S29AL004D_00_A1
See
Chip Erase Command Sequence
Table 5 on page 24
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See
these status bits. When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched.
A d v a n c e
for program command sequence.
Increment Address
Write Operation Status‚ on page 26
Figure 3. Program Operation
I n f o r m a t i o n
in progress
Embedded
algorithm
Program
Table on page 24
S29AL004D
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
shows the address and data
Yes
Yes
for information on
No
21