upd17107 Renesas Electronics Corporation., upd17107 Datasheet - Page 37

• Manufacturer Part Number: upd17107
• Description: 4 Bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

7. STANDBY FUNCTIONS
7.1 HALT MODE
mode can be entered with the HALT instruction, and can be released by a reset signal (RESET) or high-level input
to the P0B
wait for the system clock oscillation to settle. The instruction immediately after the HALT instruction is executed.
at address 0H.
7.2 STOP MODE
mode can be entered with the STOP instruction, and can be released by a reset signal (RESET) or high-level input
to the P0B
instruction immediately after the STOP instruction.
starts at address 0H.
7.3 SETTING AND RELEASING THE STANDBY MODES
(1) Setting and releasing the HALT mode
(2) Setting and releasing the STOP mode
X
The PD17107(A1) provides two standby modes, the HALT mode and the STOP mode.
The HALT mode stops the program counter (PC) while allowing the system clock to continue operating. The HALT
When the HALT mode is released forcibly by the reset signal (RESET), normal reset occurs, and the program starts
The STOP mode stops the system clock oscillation so that data can be retained at low power voltage. The STOP
When the STOP mode is released forcibly by the reset signal (RESET), normal reset occurs, and the program
0
1
Conditions for releasing the HALT mode are selected with the least significant bit of the operand in the HALT
instruction as shown in Table 7-1. The high-order three bits of the operand must be set to 0.
Conditions to release the STOP mode are selected with the least significant bit of the operand in the STOP
instruction as shown in Table 7-2. The high-order three bits of the operand must be set to 0.
HALT 000XB
After executing a HALT instruction, the system enters the HALT mode unconditionally.
The mode can be released only by the reset signal (RESET). After the mode is released, the program starts at
address 0H.
When a HALT instruction is executed with the P0B
mode can be released by the reset signal (RESET). When the mode is released, the program starts at address 0H.
This mode can also be released when a high-level signal is applied to the P0B
with the instruction immediately after the HALT instruction.
When a HALT instruction is executed with the P0B
NOP instruction) and the system does not enter the HALT mode.
0
1
pin. When the HALT mode is released by a high-level signal input to the P0B
pin. When the mode is released by a high-level signal input to the P0B
4-bit data in the operand
Table 7-1 Conditions for Setting/Releasing the HALT Mode
Conditions for setting/releasing the HALT mode
0
0
pin being at low level, the system enters the HALT mode. The
pin being at high level, the instruction is ignored (regarded as a
0
pin. In this case, the program starts
1
pin, the program starts with the
0
pin, the system does not
PD17107(A1)
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