upd16835 Renesas Electronics Corporation., upd16835 Datasheet - Page 25

• Manufacturer Part Number: upd16835
• Description: Monolithic Quad H Bridge Driver Circuit
• Manufacturer: Renesas Electronics Corporation.

PULSE CHECK
start point drive wait
(original oscillation)
1st byte
ENABLE OUT
CHECK SUM
Start point wait +
Chopping pulse
Start point wait
EXP0 to EXP3
PULSE GATE
PULSE OUT
8th byte
OSC
RESET
SDATA
LATCH
DATA
SCLK
(FF1)
(FF2)
(FF3)
(FF7)
Note 1
Note 2
Note 3
OUT
V
D
Data is held at rising edge of SCLK.
EXP: 1
Initial
(LSB)
D0
I
1
Initialization
Output by chopping
setting of I1 data
Outputs high level for standard data while a
pulse output signal exists (LATCH cycle)
Input at rising
edge of RESET
Dummy data
Output by EXP
setting of I1 data
D1
High level because
data is normal.
D2
Standard
EXP
ENABLE: 0
Outputs high level while
pulse is being generated
S
D3
1
: 0
Output by
I1 data
Output by
I1 data
Output by EXP
setting of S1 data
D4
S
Output by S2
data setting
2
DATA output
D5
S
2
D6
Low level because
data is abnormal.
Standard
EXP
ENABLE: 1
D7
: 1
Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low
S
3
2. FF7 is an output signal that is used to check for the presence or absence
3. CHECK SUM output is updated at the falling edge of LATCH.
No pulse output because
data is erroneous
Standard
EXP : 1
error DATA
Output by EXP
setting of S2DATA
to high, and at the falling edge of FF2 when the level changes from high
to low.
of a pulse in the standard data, is updated at the falling edge of LATCH
and reset once at the rising edge of LATCH. If CHECK SUM is other than
“00H”, FF7 goes low, inhibiting pulse output, even if a pulse is generated.
Pulse error
S
4
DATA output
S
4
Standard
EXP
ENABLE: 1
Restore to high level because
data is normal.
: 0
Output by S5
data setting
Standard
EXP
ENABLE: 0
S
5
: 1
Enable