upd72862 Renesas Electronics Corporation., upd72862 Datasheet
upd72862
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upd72862 Summary of contents
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IEEE1394 OHCI HOST CONTROLLER The PD72862 is IEEE1394 OHCI-Link controller. The PD72862 complies with the P1394a draft 2.0 specifications and works up to 400 Mbps. It supports both of the Cardbus interface and the PCI bus interface. FEATURES • Compliant ...
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Firewarden™ ROADMAP IEEE1394-1995 Core Development OHCI Link PD72860 Hotline Link 1997 1998 2 Firewarden Series OHCI Link PD72862 1 Chip OHCI+PHY OHCI Link PD72870A PD72861 1 Chip OHCI+PHY PD72870 1999 2000 Data Sheet S14265EJ2V0DS00 PD72862 PC Application 800M/1.6G p1394.b Link ...
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BLOCK DIAGRAM PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap OPCI Internal Bus PCIS_CNT OPCIBUS_ARB ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register CSR : Control and Status Registers IOREG : ...
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PIN CONFIGURATION (Top View) Though the current implementation of the PD72862 includes signal pins for debugging and testing purpose, the package remains a cost efficient 100-pin TQFP package. • 100-pin plastic TQFP (Fine pitch) (14 x 14) 3. ...
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PIN NAME AD0-AD31 : PCI Multiplexed Address and Data CARD_ON : PCI/Card Select CBE0-CBE3 : Command/Byte Enables CIS_ON : CIS Register ON CLKRUN : PCICLK Running CTL0, CTL1 : PHY/Link Bi-directional Control DEVSEL : Device Select DIRECT : Auxiliary PHY/Link ...
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PIN FUNCTIONS ..................................................................................................................................... 8 1.1 PCI Bus Interface Signals: (52 pins) .............................................................................................. 8 1.2 PCI/Cardbus Select Signals: (2 pins) ............................................................................................. 9 1.3 PHY/Link Interface Signals: (15 pins) .......................................................................................... 10 1.4 Serial ROM Interface Signals: (3 pins) ......................................................................................... 10 1.5 ...
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ELECTRICAL SPECIFICATIONS ......................................................................................................... 27 5. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 30 6. PACKAGE DRAWING .......................................................................................................................... 31 7. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 32 Data Sheet S14265EJ2V0DS00 PD72862 7 ...
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PIN FUNCTIONS 1.1 PCI Bus Interface Signals: (52 pins) Name I/O Pin No PAR I/O 18 PCI/Cardbus AD0-AD31 I/O 2- PCI/Cardbus 21-24, 27-30, 33-36, 39-42, 86-91, 93, 94, 98, 99 CBE0-CBE3 I 9, 20, - ...
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Name I/O Pin No PME O 79 PCI/Cardbus CLKRUN I/O 78 PCI/Cardbus INTA O 80 PCI/Cardbus PERR I/O 16 PCI/Cardbus SERR O 17 PCI/Cardbus PRST PCLK 1.2 PCI/Cardbus Select Signals: (2 pins) ...
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PHY/Link Interface Signals: (15 pins) Name I/O Pin No D0-D7 I/O 59-62, 9mA 64-67 CTL0,CTL1 I/O 69, 70 9mA LREQ O 73 9mA LINKON LPS O 74 9mA SCLK DIRECT I ...
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REGISTER DESCRIPTIONS 2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) DeviceID Status Class Code BIST Header Type Base Address 0 (OHCI Registers) Subsystem ID Expansion Rom Base Address Register 000000H Max_Lat Min_Gnt Power Management Capabilities ...
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Offset_00 VendorID Register This register identifies the manufacturer of the PD72862. The ID is assigned by the PCI_SIG committee. Bits R/W 15-0 R Constant value of 1033H. 2.1.2 Offset_02 DeviceID Register This register identifies the type of the device ...
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Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72862. “Read” and “Write” are handled somewhat differently. Bits R/W 3-0 R Reserved Constant value of 0000 New capabilities ...
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Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72862. Bits R/W 7-0 R Default value of 02H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. 2.1.6 ...
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Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the “Operation registers” (i.e. control, configuration, and status registers) of the PD72862, while the BIOS is expected to set this value during power-up reset. ...
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Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the PD72862, the NEC’s implementation of the 1394 OpenHCI specification. Bits R/W 7-0 R/W Default value of 00H. It specifies which input of the host ...
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Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72862’s Capability List. Bits ...
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CardBus Mode Configuration Register ( CARD_ON=High ) DeviceID Status Class Code BIST Header Type Base Address 0 (OHCI Registers) Base Address 1 (CardBus Status Reg) Base Address 2 (CardBus Status Reg) Subsystem ID Expansion Rom Base ...
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Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers) Bits R/W 7-0 R Constant value of 00. 31-8 R/W - (1) Function Event Register (FER) ( Base Address Bits R Write Protect (No Use). ...
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Function Reset Status Register (FRSR) ( Base Address Bits R Write Protect (No Use). Read only as ‘0’ Ready Status (No Use). Read only as ‘0’ Battery ...
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SERIAL ROM INTERFACE The PD72862 provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM. 3.1 Serial EEPROM Register Register Address Base address + 0x930 Base ...
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W_GUIDHi register (Base address + 0x938) 31 Field Bits R/W Default value W_GUIDHi 31-0 R/W Undefined (4) W_GUIDLo register (Base address + 0x93C) 31 Field Bits R/W Default value W_GUIDLo 31-0 R/W Undefined (5) Parameters Write register (Base address ...
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W_GENERAL register (Base address + 0x950 - 0x95C) 31 W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C) Field Bits R/W Default value W_GENERAL_0 - 31-0 R/W Undefined W_GENERAL_3 (7) W_PHYS register (Base address + 0x960) 31 ...
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Table 3-1. Serial EEPROM Memory Map Byte address ...
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Load Control GROM_EN CARD_ON CIS_ON loading W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable are loaded All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - ...
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Notes 5. If none of W_programPhyEnable, W_aPhyEnhanceEnable in serial EEPROM are changed, (15)-(17) transactions don't need none of W_CIS_0 - W_CIS_31 in serial EEPROM are changed, (18)-(21) transactions don't need. 26 Data Sheet S14265EJ2V0DS00 PD72862 ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the ...
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DC Characteristics (V = 3 Parameter High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current Supply current PCI interface High-level input voltage Low-level input voltage High-level output current Low-level ...
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AC Characteristics PCI Interface See PCI local bus specification Revision 2.1. PHY/Link Interface Parameter D,CTL setup time to SCLK rise D,CTL hold time to SCLK rise SCLK rise to D,CTL,LREQ out SCLK cycle time PHY/Link Interface Timing SCLK t D ...
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APPLICATION CIRCUIT EXAMPLE 0.1 F 0 ...
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PACKAGE DRAWING 100-PIN PLASTIC TQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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RECOMMENDED SOLDERING CONDITIONS The PD72850A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other ...
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Data Sheet S14265EJ2V0DS00 PD72862 33 ...
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Data Sheet S14265EJ2V0DS00 PD72862 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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EEPROM and Firewarden are trademarks of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from ...