t431616a TM Technology Inc., t431616a Datasheet - Page 17

• Manufacturer Part Number: t431616a
• Description: 1m X 16 Sdram - Taiwan Memory Technology
• Manufacturer: TM Technology Inc.

Read & Write Cycle at Same Bank @Burst Length = 4
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
Taiwan Memory Technology, Inc. reserves the right P.17
to change products or specifications without notice.
tm
D Q
C L O C K
A 1 0 / A P
A D D R
C K E
R A S
C A S
D Q M
C L = 2
C L = 3
C S
B A
W E
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
3. Access time from Row active command.
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
available after Row precharge. Last valid output will be Hi-Z(
Burst can’t end in Full Page Mode.
0
CH
TE
R a
R a
1
A c t i v e ( A -
B a n k )
R o w
2
t
R C D
* N o t e 3
t
R A C
3
* N o t e 3
C a 0
4
R e a d ( A -
B a n k )
5
t
t
S A C
R C
Q a 0
6
* N o t e 1
t
t
O H
S A C
Q a 1
Q a 0
7
t
O H
Q a 2
Q a 1
H I G H
8
* N o t e 2
t
P r e c h a r g
Q a 3
Q a 2
CC
B a n k )
e ( A -
9
t
*(
S H Z
t
Q a 3
RCD
1 0
t
S H Z
* N o t e 4
+CAS latency-1)+
1 1
R o w A c t i v e
( A - B n a k )
* N o t e 4
R b
R b
1 2
t
SHZ
1 3
W r i t e ( A -
C b 0
D b 0
D b 0
B n a k )
) after the clock.
1 4
t
D b 1
D b 1
SAC
Publication Date: DEC. 2000
1 5
D b 2
D b 2
1 6
D b 3
D b 3
1 7
T431616A
t
t
R D L
R D L
1 8
P r e c h a r g e
( a - B n a k )
Revision: C
: D o n 't c a r e
1 9