sm5330a Seiko NPC Corp., sm5330a Datasheet
sm5330a
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sm5330a Summary of contents
Page 1
... OVERVIEW The SM5330A is a 4-system input switching 3-channel video filter with 5th-order lowpass filter built-in. The lowpass filter cutoff frequency range is 5MHz to 13MHz (SD mode) or 16MHz to 40MHz (HD mode), con trolled using BUS . The lowpass filter enables the device to be utilized in the analog input stage of video signal equipment, functioning as an ADC system anti-aliasing fi ...
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... IN2_SW /off IN2_1 IN2_2 IN2_3 Clamp Clamp /Bias /off IN3_1 IN3_2 IN3_3 Clamp Clamp /Bias /off IN4_1 IN4_2 IN4_3 SM5330A I/O_1 I/O_0 VCC VREF IREF Control Logic Reference Comparator Clamp /Bias /Bias /off /off CH-1 Clamp /Bias /Bias /off /off Clamp ...
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... VREF O 33 GND GND 34 IN1_1 I 35 IN1_2 I 36 IN1_3 I SM5330A *2 A/D Description A System 3 channel 1 video signal input pin A System 3 channel 2 video signal input pin A System 3 channel 3 video signal input pin A Analog ground pin A System 4 channel 1 video signal input pin A System 4 channel 2 video signal input pin ...
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... IN2_L2 I 47 IN2_L3 I 48 IN2_SW I *1. I: input, O: output, P: Power supply, GND: Ground *2. A: analog, D: digital SM5330A *2 A/D Description D System 1 D-terminal signal discriminator input pin. 3-state input D System 1 D-terminal signal discriminator input pin D System 1 D-terminal signal discriminator input pin. 3-state input D System 1 D-terminal signal discriminator input pin ...
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... I 1 IN3_1 2 IN3_2 3 IN3_3 5 IN4_1 6 IN4_2 7 IN4_3 9 DAC_0 O 11 DAC_1 10 TEST I 13 YOUT O SM5330A Equivalent circuit VCC 45Ω INn_n 20kΩ GND VCC 5kΩ 5kΩ DAC_n GND VCCD 180Ω TEST GND VCC 200Ω YOUT GND SEIKO NPC CORPORATION —5 ...
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... Number Name I/O 15 OUT_3 19 OUT_2 O 21 OUT_1 24 I/O_0 I/O 25 I/O_1 26 ADS I 27 SCL I SM5330A Equivalent circuit VCC OUT_n GND 671Ω 500Ω VCCD 180Ω I/O_n DGND VCCD 100kΩ 180Ω ADS 100kΩ DGND VDD 180Ω SCL DGND SEIKO NPC CORPORATION —6 ...
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... O 32 VREF O 37 IN1_L1 38 IN1_L2 39 IN1_L3 40 IN1_SW I 45 IN2_L1 46 IN2_L2 47 IN2_L3 48 IN2_SW *1. I: input, O: output SM5330A Equivalent circuit VDD 180Ω SDA DGND VCC 70Ω 200Ω IREF GND VCC VREF GND VCC 180Ω INn_Ln GND SEIKO NPC CORPORATION —7 ...
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... LOW-level input leakage current 1 I LL1 HIGH-level input leakage current 2 I LH2 LOW-level input leakage current 2 I LL2 LOW-level output voltage V OL SM5330A Condition VCC, VDD, VCCD GND – 0 θ ° C/W ( ° C, PCB ja wiring density: 100%, 0.5m/s air flow) Condition VCC, VCCD VDD Wiring density: 100%, air fl ...
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... FCM = H, FCSET = 3Fh, unless otherwise noted. Parameter Symbol Clamp voltage V CLAMP Bias voltage V BIAS Input resistance R IBIAS Input amplitude 1 V AI1 Input amplitude 2 V AI2 Input DC voltage range V IDC SM5330A Condition min 0 0.6 1.3 0.6 0.6 0 100 − − 0.6 1.3 – SU;DAT HIGH SU ...
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... Cutoff frequency 4fc attenuation A SB SM5330A = 1.0Vp- Condition min OUT_1, OUT_2, OUT_3 5.5 Between OUT_1, OUT_2, and OUT_3 Clamp input, THD < 1.0% Bias input, THD < 1.0% 0.5Vp-p input, fin = 1MHz, between 2 channels 0.5Vp-p input, fin = 1MHz, between each input system ...
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... IN3_PB 1µF IN3_Y 1µF IN4_PR 1µF IN4_PB 1µF IN4_Y Note. This is a circuit only for the evaluation board of an electric characteristics. (It is not a recommended application circuit.) SM5330A Condition DAC_0, DAC_1, V – n–1 – 255 (V – V )/128 191 ...
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... The write sequence is: SM5330A slave address → specific control register sub-address → write data. Data can be written to the SM5330A in successive bytes, as the sub-address for the register is incremented automatically after each byte. However, if the sub-address exceeds the address of the last register (04h), data write operation to the SM5330A register stops and the acknowledge signal is not returned ...
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... Slave Address The 7-bit slave address is selected using the ADS pin. When ADS = “L” the address is 48h, when ADS = “H” the address is 49h, and when ADS = “Z” (open) the address is 4Ah. A maximum of three SM5330A devices 2 can be connected to one I C BUS simultaneously, and controlled independently by setting the slave address of each using the ADS pin ...
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... This setting also determines the system that performs status register D-terminal discrim- ination. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, these bits are set to “1” so that the output is high impedance. SM5330A bit3 bit2 ...
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... Name default Value Sets the DAC_0 and DAC_1 pins output voltage, respectively. Status Register The SM5330A has a 3-byte status register. STATUS REGISTER MAP Addr. bit7 bit6 bit5 bit4 − − − 00h 01h L1 − − − ...
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... Value Returns the D-terminal connection status information. SM5330A bit3 bit2 bit1 bit0 L2 L3 Decode INn_Ln input selected series via INSEL register (L1: screen ruling) INn_L1 input "L" (< 0.8V) means "480" INn_L1 input "M" (1.4 to 2.4V) means "720" INn_L1 input "H" (> 3.5V) means "1080" ...
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... The SM5330A has a 4-system input switch built-in, and the system selected by the control register INSEL bits is input to the lowpass filter. When muting is selected (INSEL = 000b), the signal is not input to the lowpass fil- ter and the output pins are DC level. ...
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... Lowpass Filter The SM5330A has a 5th-order lowpass filter built-in, with a cutoff frequency selectable from 64 levels each for SD/HD mode controlled using the I and shown in table 2. Figure 3. FCSET setting vs. Cutoff frequency Table 2. Cutoff frequency vs. FCDATA (R FCSET FCDATA fc [MHz] FCDATA (hex 5. 5.24 17 ...
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... VREF Pin The VREF pin is the internal reference voltage output recommended that a capacitor be connected between VREF and GND to ensure SM5330A operating stability. The recommended value is 1µF. The voltage on VREF is output in normal operating mode and during output muting. D-Terminal Discrimination Function The D-terminal signal discrimination result can be read using the I the state of IN1_SW, and the SW2 bit returns the state of IN2_SW ...
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... Setting the Slave Address to 49h When the ADS pin is open-circuit, the slave address is set to 49h. When open, however, a large external spike noise or other interference can cause a malfunction. An external resistor should be connected to ADS as shown in figure 4 for protection. SM5330A IN1_L1 I/O_0 IN1_L2 VCCD ...
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... Frequency [MHz] Figure 7. Gain and Group delay characteristics (FCDATA = 128 FCDATA = 191 –12 FCDATA = 128 –24 FCDATA = 63 FCDATA = 0 –36 –48 –60 0 1.0 10.0 Frequency [MHz] Figure 9. Gain vs. FCDATA SM5330A = 1.0Vp- 1.8kΩ ISET 180 12 150 0 120 –12 90 –24 60 –36 30 –48 – ...
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... Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SM5330A SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, ...