sm5901af Seiko NPC Corp., sm5901af Datasheet
sm5901af
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sm5901af Summary of contents
Page 1
... Microcontroller interface for external control using 5 extension I/O pins - +2.7 to +3.3 V wide operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately 3 longer (65 system clock pulses) continuous LOW-level reset - 44-pin QFP package (0.8 mm pin pitch) SM5901AF ...
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... Package dimensions 44-pin QFP Pinout (Top View) NTEST1 NTEST2 YSRDATA SM5901AF (Unit: mm 13.20 0. 10.00 0.20 0.35 0.80 VDD2 1 UC1 2 UC2 3 UC3 4 UC4 5 VSS2 CLK 9 VSS1 0.80 0.20 NWE NCAS2 28 NTEST4 27 26 YMCLK 25 YMDATA 24 YMLD 23 YDMUTE ...
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... Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when a input mode) And in case that only internal 1M DRAM is used, 28, 33, 34 pin are high impedance, and pin are input pull up mode. SM5901AF Function VDD supply pin Microcontroller interface extension I/O 1 ...
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... Input current CLK (*3,4) Input leakage current (*2,3,4,5) (*2,5) Output leakage current (*7) (*A) VDD = 3 V, CLK input frequency f = 384fs = 16.9344 MHz, all outputs unloaded, XTI SHPRF: Shock-proof, typical values are for VDD = 3 V. SM5901AF (VSS = 0V, VDD pin voltage = Rating Unit - 0 ...
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... Pin function Pin name (*6) Pin function Pin name (*7) Pin function Pin name SM5901AF Clock input pin (AC input) CLK Schmitt input pins YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET, YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK Schmitt input pin with pull-up NTEST1, NTEST2, NTEST3, NTEST4 ...
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... Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. YSCK YSRDATA YLRCK SM5901AF Symbol Condition System clock t CWH ...
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... Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth t Note. is the system clock (CLK) input (384fs) cycle time ns, (min) = 3.8 s when fs = 44.1 kHz CY NRST VDD NRESET SM5901AF Symbol Rating Min MCWL MCWH ...
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... Input hold NWE pulsewidth NWE falling edge to NCAS2 falling edge Refresh cycle (fs = 44.1 kHz playback) Memory system ON Decode sequence operation (RDEN=H) t Note. is the system clock (CLK) input (384fs) cycle time. CY SM5901AF Symbol Condition Min load SCOW load SCOY load ...
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... DRAM access timing (when external DRAM is used) NRAS NCAS2 (DRAM2 SELECT) t RADS (WRITE (READ) NWE (WRITE) SM5901AF t RASL RCD CASL RADH CADS CWDS CWDH ...
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... SM5901 YBLKCK Control YFCLK Input 1 YFLAG YMDATA YMCLK Microcont- roller Interface YMLD ZSENSE General UC1 to UC4 Port YDMUTE Control NRESET Input 2 NTEST SM5901AF Output Interface Attenuator Compression Through Mode Mode Decoder 1M DRAM DRAM Interface Input Interface Input Buffer Encoder ...
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... YMDATA YMCLK YMLD ZSENSE SM5901AF The operating sequences are controlled using com- mands from a microcontroller. In the case of a read command from the microcon- troller, bit serial data is output (ZSENSE) synchro- nized to the bit clock input (YMCLK). DATA 8bit COMMAND 8bit ...
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... UC4WD D2 UC3WD D1 UC2WD D0 UC1WD SM5901AF Function Encode sequence start/stop Write address reset Decode sequence start/stop Read address reset MSDCN2=H, MSDCN1=H: 3-pair comparison start MSDCN2=H, MSDCN1=L: 2-pair comparison start MSDCN2=L, MSDCN1=H: Direct-connect start MSDCN2=L, MSDCN1=L: Connect operation stop Q data valid ...
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... YFCKP D3 COMPFB D2 COMP6B D1 COMP5B D0 COMP4B When the number of compression bits is set incorrectly (2 or more bits are set all bits are set to 0), SM5901AF Function Attenuator enable Forced muting (changes instantaneously) Soft muting (changes smoothly when ON only) Function - 1 MSB 2 - ...
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... Valid data empty state (Always HIGH when RA exceeds VWA) S6 OVFL Write overflow state (Always HIGH when WA exceeds RA) S5 ENCOD S4 DECOD SM5901AF Function Function Encode sequence operating state Decode sequence operating state 90hex = 1001 0000 HIGH-level state Exceeded DRAM overflow Compare-connect sequence operating Encoding stopped ...
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... OR the output data from a pin configured as an output port using the 82H command.) Bit Name UC4RD S2 UC3RD S1 UC2RD S0 UC1RD SM5901AF Function 2M bits 1M bits 512K bits 256K bits 128K bits 64K bits 32K bits 16K bits 8K bits 4K bits 2K bits 1K bits 512 bits ...
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... Meaning 90H bit 1 Set Reset SM5901AF - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. FLAG6 set conditions When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L ...
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... Meaning 91H bit 4 Set Reset SM5901AF - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address (address from which the next read would take place) - Whenever the above does not apply - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA) ...
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... MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Decode sequence stops 81H (I/O setting on extension I/O) 82H (Setting output data on extension I/O) SM5901AF -MSRACL When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 When 1 and 1: 3-pair compare-connect sequence ...
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... YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 SM5901AF - SOFT (soft muting) When 1: Outputs are smoothly muted to 0. When 0: No muting. Soft mute release occurs instantaneously ...
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... Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. SM5901AF troller command 80H. This mode comprises the following 3 sequences. 3. The encoder, after the most suitable predicting filter type and quantization steps have been deter- mined, performs APC encoding and then writes to external DRAM ...
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... YBLKCK Microcontroller data set Refer to Microcontroller interface VWA SM5901AF VWA 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV com- mand (80H). 3.When the WAQV command is received, VWA is updated according to the previously latched WA. ...
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... When YFLAG=LOW 4 1 When YFLAG=HIGH SM5901AF encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depend- ing on the YFLGS flag and YFCKP flag (85H com- mand). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low ...
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... Compare-connect sequence stop If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2 input from the micro- controller, compare-connect sequence stops. SM5901AF In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to con- form with the valid data. At this point, the encode sequence is re-started and data is written to VWA ...
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... Data compression mode 4 bit 5 bit 6 bit Full bit SM5901AF - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued ...
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... WA CAS 3FE RA CAS 3FD Encode compression mode Decode compression mode ZSRDATA (note) CAS-000 is connect data. SM5901AF immediately after input of the 85H command, but it is performed at the following timing. After changing the mode, zero data of one block is output. 3FF 001 002 3FE ...
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... But when the ATT flag is 0 (Datt = 256), there is no attenuation. set 1 Gain set 2 SM5901AF LOW. Accordingly, to provide for the largest possi- ble jitter margin necessary that the YLRCK clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs. ...
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... When the CMP12 flag is set to 1, the least signifi- cant 4 bits of the 16-bit comparison connection input data are discarded and comparison connec- tion is performed using the remaining 12 bits. SM5901AF Conversely, mute is released when the SOFT flag this case, the attenuation counter instanta- neously increases. The attenuation register takes on the value when the ATT flag was 1 ...
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... Timing charts Input timing (YSCK, YSRDATA, YLRCK) YSCK YSRDATA YLRCK Output timing (ZSCK, ZSRDATA, ZLRCK) 1 ZSCK ZSRDATA ZLRCK SM5901AF 16 L channel 1/2fs channel 1/ channel 48 R channel ...
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... SSELECT (WRITE) NWE DRAM read timing (NRAS, NCA2, NWE A8 D3) Read timing (when external DRAM is used) NRAS NCAS2 (DRAM2 SSELECT (READ) NWE SM5901AF t RASL t t RCD CASL RADS CADS RADH t t CWDS ...
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... D/A converter note1 - When external DRAM is used, the DRAM OE pins should be tied LOW. note 2 When CXD 2517 (Sony) is used Set 85H of microcontroller comand (option setting) as setting YFLAG take in; D5: YFLAGS= 1 D4: YFCKP= 0 SM5901AF SM5901 YMDATA YMCLK YMLD ZSENSE UC1 to UC4 YBLKCK NRAS ...
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... Customers shall not export, directly or indirect- ly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM5901AF reserves the right to make changes to the products described in this data sheet in order to NIPPON PRECISION CIRCUITS INC. ...