ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 104

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. See Section
7.8.2.4.
Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8kHz output on the FSYNC pin. See Section
7.8.2.4.
Bits 3 to 0: Output Frequency of OC7 (OFREQ7[3:0]). This field specifies the frequency of output clock output
OC7. The frequencies of the T0 APLL and T4 APLL are configured in the
Digital1 and Digital2 frequencies are configured in the
is controlled by the value of the OCR5.AOF7 bit.
AOF7 = 0: (standard decodes)
AOF7 = 1: (alternate decodes)
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = Disabled, driven low
1 = Enabled, output is 2kHz
0 = Disabled, driven low
1 = Enabled, output is 8kHz
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = T0 APLL frequency divided by 2
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e., low)
0001 = T4 APLL frequency divided by 5
0010 = T4 APLL frequency divided by 2
0011 = T4 APLL frequency
0100 = T0 APLL2 frequency divided by 5
0101 = T0 APLL2 frequency divided by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
MFSEN
7
1
Table
FSEN
6
1
OCR4
Output Configuration Register 4
63h
7-9)
—
5
0
MCR7
—
4
0
register. See Section 7.8.2.3. The decode of this field
3
0
T0CR1
2
1
OFREQ7[3:0]
and
T4CR1
1
1
registers. The
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0
0