ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 22

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately 8, 4, 2, or 1 units/second.
A leak is prevented when a fill event occurs in the same interval.
When the value of an accumulator reaches the alarm threshold
set to 1 in the
accumulator reaches the alarm clear threshold
ACT bit. The accumulator cannot increment past the size of the bucket specified in the
rate of the accumulator is specified in the
registers must have the following relationship at all times:
When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the x
in LBxU is the leaky bucket configuration number 0 to 3). The minimum time to clear an activity alarm in seconds is
2^LBxD * (LBxS – LBxL) / 8. For example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The minimum
time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm would be
2^0 * (10 – 1) / 8 = 1.125 seconds.
7.5.3 Selected Reference Activity Monitoring
The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected
reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from
the reference until the reference is available again. By design, the regular input clock activity monitor (Section
7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz,
125MHz, 62.5MHz, 25MHz, and 10MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an
interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin
follows the state of the SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference
switch (see Section 7.6.4). When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during
no-activity events. If the selected reference becomes available again before any alarms are declared by the activity
monitor, the T0 DPLL continues to track the selected reference using nearest edge locking (±180°) to avoid cycle
slips. When NALOL = 1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL
state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt
request if enabled. If the selected reference becomes available again before any alarms are declared by the activity
monitor, the T0 DPLL tracks the selected reference using phase/frequency locking (±360°) until phase lock is
reestablished.
When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the
PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If
NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an
interrupt request if enabled.
Rev: 012108
____________________________________________________________________________________________ DS3102
I SR
4
registers, and the clock is marked invalid in the
LBxD
(LBxL
register. The values stored in the leaky bucket configuration
register), the activity alarm is cleared by clearing the clock’s
LBxS
(LBxU
≥
LBxU
register), the corresponding ACT alarm bit is
> LBxL.
VALSR
registers. When the value of an
LBxS
register. The decay
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