S25FL040A Meet Spansion Inc., S25FL040A Datasheet
S25FL040A
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S25FL040A Summary of contents
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... Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number S25FL040A_00 Revision B Amendment 2 S25FL040A Cover Sheet Issue Date July 2, 2007 ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL040A S25FL040A_00_B2 July 2, 2007 ...
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... RES command one-byte electronic signature for backward compatibility General Description The S25FL040A is a 3.0 Volt (2 3.6 V), single-power-supply Flash memory device with with erasable sectors for boot code and parameter storage. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3 ...
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... SOA 008—Narrow 8-pin Plastic Small Outline 150 mils Body Width Package . . . . . . . . . . . 36 17.2 SOC 008—Wide 8-pin Plastic Small Outline 208 mils Body Width Package 17.3 USON mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL040A S25FL040A_00_B2 July 2, 2007 ...
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... Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 12.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 16.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 16.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 16.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD July 2, 2007 S25FL040A_00_B2 S25FL040A 5 ...
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... Tables Table 5.1 S25FL040A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 7.1 S25FL040A Protected Area Sizes (Top Boot .13 Table 7.2 S25FL040A Protected Area Sizes (Bottom Boot .13 Table 7.3 S25FL040A Protected Area Sizes (Uniform Sector .14 Table 8.1 S25FL040A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 8.2 S25FL040A Sector Address Table (Top Boot .15 Table 8.3 S25FL040A Sector Address Table (Bottom Boot .15 Table 8 ...
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... Block Diagram SRAM Logic July 2, 2007 S25FL040A_00_B2 Array - L RD DATA PATH IO S25FL040A Array - ...
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... Figure 2.1 8-pin Plastic Small Outline Package (SO 150 mil, SO 208 mil VCC HOLD# 3 SCK GND SI Figure 2.2 8L USON ( mm) Package 8 CS# VCC HOLD SCK W# 4 GND SI 5 S25FL040A S25FL040A_00_B2 July 2, 2007 ...
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... CS# (Chip Select) HOLD# (Hold) W# (Write Protect GND 4. Logic Symbol July 2, 2007 S25FL040A_00_B2 I/O Output Transfers data serially out of the device on the falling edge of SCK. Transfers data serially into the device. Device latches commands, addresses, and Input program data the rising edge of SCK. ...
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... DEVICE FAMILY S25FL TM Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL040A Valid Combinations Table S25FL040A Valid Combinations Package & Speed Option Temperature MAI, MFI, 0L VAI, VFI, NAI, NFI S25FL040A PACKING TYPE (Note 1) 0 ...
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... The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL CPHA Mode Mode 3 July 2, 2007 S25FL040A_00_B2 Figure 6.2 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK SCK SO SI ...
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... Status Register The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.3, S25FL040A Status Register on page Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. ...
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... SA12:SA7 00000–6FFFF 60000–7FFFF (7) SA12:SA6 00000–5FFFF 40000–7FFFF (9) SA12:SA4 00000–3FFFF 00000–7FFFF (13) SA12:SA0 00000–7FFFF (13) SA12:SA0 Table 7.2 S25FL040A Protected Area Sizes (Bottom Boot) Memory Array Protected Protected Unprotected Sectors Address Range None (0) 00000–7FFFF 00000–03FFF (1) SA0 04000–7FFFF 00000– ...
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... Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. SCK HOLD Table 7.3 S25FL040A Protected Area Sizes (Uniform Sector) Memory Array Protected Protected Unprotected Address Range Sectors Address Range ...
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... Byte 50000h 64K Byte 40000h 64K Byte 30000h 64K Byte 20000h 64K Byte 10000h 64K Byte 00000h Table 8.3 S25FL040A Sector Address Table (Bottom Boot) Size 64K Byte 70000h 64K Byte 60000h 64K Byte 50000h 64K Byte 40000h 64K Byte 30000h ...
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... The READ command is terminated by driving CS# high at any time during data output. The device rejects any READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted Table 8.4 S25FL040A Sector Address Table (Uniform Sectors) 070000h 060000h 050000h 040000h 030000h ...
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... FAST_READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL040A_00_B2 Figure 9.1 Read Data Bytes (READ) Command Sequence ...
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... Information Sector Type (1st Byte) Uniform Top Boot 01h Bottom Boot S25FL040A 9. Device Identification Device Identification Memory Type Memory Capacity (2nd Byte) (3rd Byte) 02h 12h 02h 25h 02h 26h S25FL040A_00_B2 July 2, 2007 ...
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... Read Identification (Read_ID) [RDID Alternate] The READ_ID instruction provides the S25FL040A manufacturer and device information. This command should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The device information can be read from by writing the 8-bit command (90H) followed by address bits. ...
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... Figure 9.5 Write Enable (WREN) Command Sequence Mode 3 Mode 0 Command Hi-Z Figure 9.6) resets the Write Enable Latch (WEL) bit which Figure 9.6 Write Disable (WRDI) Command Sequence CS Mode 3 SCK Mode 0 Command SI Hi-Z SO S25FL040A S25FL040A_00_B2 July 2, 2007 ...
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... The Write Status Register (WRSR) command controls these bits, which are non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see July 2, 2007 S25FL040A_00_B2 Table 9.3 S25FL040A Status Register Bit Function 1 = Protects when W# is low Status Register Write Disable protection, even when W# is low — ...
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... Protected Area Unprotected Area (See Note) (See Note) Ready to accept Page Protected against program Program and Sector Erase and erase commands commands Ready to accept Page Protected against program Program and Sector Erase and erase commands commands Table 7.1 on page 13. S25FL040A_00_B2 July 2, 2007 ...
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... The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see CS# Mode 3 SCK Mode SCK MSB July 2, 2007 S25FL040A_00_B2 and Table 9.5. Table 7.1 on page 13). Figure 9.9 Page Program (PP) Command Sequence ...
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... Table 7.1 on page 13 valid address for the SE command. CS# must be Table 7.1 on page 13). Figure 9.10 Sector Erase (SE) Command Sequence Command 23 22 MSB S25FL040A Figure 9.10 . The Status Register may 24-bit Address S25FL040A_00_B2 July 2, 2007 and ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see on page 13). Otherwise, the device ignores the command. CS# SCK SI SO July 2, 2007 S25FL040A_00_B2 Figure 9.11 Bulk Erase (BE) Command Sequence Mode ...
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... (see Table 14.1 on page 32). DP 9.13 and 9.13.1). Figure 9.12 Deep Power Down (DP) Command Sequence Command Standby Mode S25FL040A Figure 9.12 and Table 9.5. the device enters the DP mode and current DP Deep Power-down Mode S25FL040A_00_B2 July 2, 2007 ...
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... Figure 9.13 Release from Deep Power Down (RES) Command Sequence CS# Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL040A_00_B2 Figure 9.13 after the 8-bit RES command byte. The device transitions RES(max) (see Table 16.1 on page RES ...
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... Figure 9.14 Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence Dummy Bytes MSB Deep Power-down Mode S25FL040A t RES MSB Electronic ID out S25FL040A_00_B2 July 2, 2007 , as RES Standby Mode ...
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... Saving RES Notes 1. The S25FL040A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (12h for uniform sector, 25h for top boot, 26h for bottom boot). 2. The S25FL040A has an Electronic Signature ID of 12h. July 2, 2007 S25FL040A_00_B2 ...
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... Figure 10.1 Power-Up Timing Diagram V cc (max) (min Table 10.1 Power-Up Timing Characteristics Parameter V (minimum (min) to device operation CC S25FL040A reaches the allowable values as follows CC rises to the threshold at power-down, all CC Full Device Access Time Min Max 2.7 10 S25FL040A_00_B2 July 2, 2007 CC feed. Unit V ms ...
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... Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 13. Operating Ranges Ambient Operating Temperature (T Positive Power Supply Note Operating ranges define those limits between which functionality of the device is guaranteed. July 2, 2007 S25FL040A_00_B2 Operating Ranges section of this document is not implied. Device Table 12.1 Absolute Maximum Ratings Description 12 ...
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... 0.4 CC min V – 0 Input and Output Min Max S25FL040A_00_B2 July 2, 2007 Table 15.1 Unit µA µA µA µ Unit ...
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... Typical program and erase times assume the following conditions: 25° Under worst-case conditions of 90° Not 100% tested CS# t CSH SCK SI Hi-Z SO July 2, 2007 S25FL040A_00_B2 Table 16.1 AC Characteristics Parameter CC = 2.7V; 100,000 cycles CC Figure 16.1 SPI Mode 0 (0,0) Input Timing t ...
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... CS# SCK CS# SCK SO SI HOLD Figure 16.2 SPI Mode 0 (0,0) Output Timing Figure 16.3 HOLD# Timing S25FL040A DIS LSB OUT S25FL040A_00_B2 July 2, 2007 ...
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... Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi-Z SO July 2, 2007 S25FL040A_00_B2 WPS S25FL040A t WPH 35 ...
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... THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED FROM THE SEATING PLANE. S25FL040A WITH PLATING (b) BASE 7 METAL SECTION A 0.07 R MIN. GAUGE PLANE A SEATING PLANE DETAIL B 3432 \ 16-038.03 \ 10.28.04 S25FL040A_00_B2 July 2, 2007 ...
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... BSC 1.27 BSC L 0.020 0.030 0.508 L1 .055 REF 1.40 REF L2 .010 BSC 0.25 BSC N 8 θ 0˚ 8˚ 0˚ θ1 5˚ 15˚ 5˚ θ2 0˚ July 2, 2007 S25FL040A_00_B2 0. SEE DETAIL E 0.10 C 0.10 C SEATING PLANE ...
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... ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. 3.50 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 8. PIN # TOP WILL BE LASER MARKED. 0.55 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 0. S25FL040A 3448\ 16-038.28 \ 04.15.05 S25FL040A_00_B2 July 2, 2007 ...
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... Changed document status from Preliminary to Full Production. RDID table Changed structure of table. Absolute Maximum Ratings Added overshoot and undershoot information. AC Characteristics Changed maximum specification for F Revision B2 (July 2, 2007) Device Operations Added a sentence to Byte or Page Programming July 2, 2007 S25FL040A_00_B2 Description . SCK S25FL040A . CC2 39 ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion Logo, MirrorBit , MirrorBit S25FL040A ® ™ ™ ™ Eclipse , ORNAND , HD-SIM S25FL040A_00_B2 July 2, 2007 ...