S25FL004A Meet Spansion Inc., S25FL004A Datasheet
S25FL004A
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S25FL004A Summary of contents
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... Data Sheet (Retired Product) This product has been retired and is not recommended for new designs. For new designs, S25FL040A supersedes S25FL004A. Please refer to the S25FL040A for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Publication Number S25FL004A_00 ...
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... This page left intentionally blank S25FL004A S25FL004A_00_B3 July 9, 2007 ...
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... This product has been retired and is not recommended for designs. For new and current designs, S25FL040A supersedes S25FL004A and is the factory-recommended migration path for this device. Please refer to the S25FL040A data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. ...
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... General Description The S25FL004A is a 3.0 Volt (2 3.6 V), single-power-supply Flash memory device. The device consists of 8 sectors, each with 512 Kb memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0 volt V The memory can be programmed 1 to 256 bytes at a time, using the Page Program command ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 17.1 SOC008—8-pin Plastic Small Outline 208-mil Body Width Package . . . . . . . . . . . . . . . . . . 31 17.2 UNE008—USON mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 July 9, 2007 S25FL004A_00_B3 S25FL004A 5 ...
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... Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10.1 Power-Up Timing Diagram Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD S25FL004A S25FL004A_00_B3 July 9, 2007 ...
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... Tables Table 5.1 S25FL004A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7.1 S25FL004A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8.1 S25FL004A Device Organization Table 8.2 S25FL004A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9.1 Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9.2 S25FL004A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9.4 Command Definitions Table 10.1 Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12.1 Absolute Maximum Ratings ...
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... Array - L RD DATA PATH IO Figure 2.1 16-pin Plastic Small Outline Package (SO CS GND 4 5 Figure 2.2 8L USON ( mm) Package 8 CS# VCC HOLD SCK W# GND S25FL004A X D Array - VCC HOLD# SCK SI S25FL004A_00_B3 July 9, 2007 ...
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... SCK (Serial Clock) CS# (Chip Select) HOLD# (Hold) W# (Write Protect GND 4. Logic Symbol July 9, 2007 S25FL004A_00_B3 I/O Output Transfers data serially out of the device on the falling edge of SCK. Transfers data serially into the device. Device latches commands, addresses, and Input program data the rising edge of SCK ...
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... DEVICE FAMILY S25FL TM Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL004A Valid Combinations Table S25FL004A Valid Combinations Package & Speed Option Temperature MAI, MFI 0L NAI, NFI S25FL004A PACKING TYPE (Note Tray ...
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... The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL CPHA Mode Mode July 9, 2007 S25FL004A_00_B3 Figure 6.2 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK SCK SO SI ...
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... Status Register The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.2, S25FL004A Status Register on page Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. ...
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... July 9, 2007 S25FL004A_00_B3 Table 7.1 S25FL004A Protected Area Sizes Memory Array Protected Address Range Protected Sectors None (0) 70000–7FFFF (1) SA7 60000–7FFFF (2) SA7:SA6 40000–7FFFF (4) SA7:SA4 00000–7FFFF (8) SA7:SA0 00000–7FFFF (8) SA7:SA0 00000– ...
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... Condition (standard use) Table 8.2 shows the starting and ending address for each Table 8.1 S25FL004A Device Organization Each Sector has Each Page has 65,536 256 — Table 8.2 S25FL004A Sector Address Table Address Range 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h S25FL004A Figure 7 ...
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... CS# 0 Mode 3 SCK Mode 0 SI Hi-Z SO July 9, 2007 S25FL004A_00_B3 Table 9.4 on page 24 lists the complete set of commands. detail the READ command sequence. The first byte specified can be at any location. Figure 9.1 Read Data Bytes (READ) Command Sequence 1 2 ...
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... SCK Figure 9.3 and S25FL004A ) presented at the SCK SCK and Table 9.4. The first byte specified can Dummy Byte MSB MSB DATA OUT 1 Table 9.4. S25FL004A_00_B3 July 9, 2007 DATA OUT 2 ...
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... Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. July 9, 2007 S25FL004A_00_B3 ...
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... Mode 3 SCK Mode 0 Command SI Hi-Z SO Figure 9.6 Table 9.2 S25FL004A Status Register Bit Function 1 = Protects when W# is low Status Register Write Disable protection, even when W# is low — Not used — Not used 000–111 = Protects upper half of address range in 5 sizes. See Block Protect Table 7 ...
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... Figure 9.6 Read Status Register (RDSR) Command Sequence Command MSB Status Register Out Table 9.2, S25FL004A Status Register on page 18 S25FL004A 15 14 MSB Status Register Out Table 7.1 shows the status register Table 9.3 on page 20 shows that W# must 19 ...
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... Note) (See Note) Protected against Ready to accept Page program and erase Program and Sector commands Erase commands Protected against Ready to accept Page program and erase Program and Sector commands Erase commands Table 7.1 on page 13. . The Status Register may PP S25FL004A_00_B3 July 9, 2007 ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute an SE command that specifies a sector that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page CS# Mode 3 SCK Mode 0 SI Hi-Z SO July 9, 2007 S25FL004A_00_B3 Figure 9.8 Page Program (PP) Command Sequence ...
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... Figure 9.10 Bulk Erase (BE) Command Sequence Mode Mode 0 Command SI Hi-Z (see Table 14.1 on page 26). DP 9.12 and 9.12.1). S25FL004A Figure 9.10 and Table 9.4 . The Status Register may BE Table 7 Figure 9.11 on page 23 and the device enters the DP mode and current DP, S25FL004A_00_B3 July 9, 2007 ...
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... DP mode to the standby mode after a delay of t the device can execute any read or write command. Figure 9.12 Release from Deep Power Down (RES) Command Sequence CS# Mode 3 SCK Mode 0 SI Hi-Z SO July 9, 2007 S25FL004A_00_B3 Figure 9.11 Deep Power Down (DP) Command Sequence ...
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... Status Register WRSR DP Power Saving RES Notes 1. The S25FL004A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (12h and Table 9.4 on page 24 for the command sequence and signature value. The ...
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... The S25FL004A has an Electronic Signature ID of 12h. 10. Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied and must not be driven low to select the device until V CC (see Figure 10.1 on page 25 At power-up power-down pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements ...
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... V to 3.6 V Table 15.1 (See Note) Min Typ. Max 2.7 3 3.6 33 MHz 3.0V MHz 16 1 –0.3 0 0.4 CC min V – 0.2 CC S25FL004A_00_B3 July 9, 2007 Unit µA µA µA µ ...
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... Test Conditions 0.8 V Input Levels 0.2 V Symbol C L July 9, 2007 S25FL004A_00_B3 Figure 15.1 AC Measurements I/O Waveform CC CC Table 15.1 Test Specifications Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage S25FL004A 0 ...
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... Min (Notes) (Notes) Unit D.C. 33 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ 100 150 ms μs 3 μs 30 1.5 (1) 3 (2) ms 0.5 (1) 3 (1) sec 3 (1) 24 (1) sec S25FL004A_00_B3 July 9, 2007 ...
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... CS# t CSH SCK SI Hi-Z SO CS# SCK CS# SCK SO SI HOLD# July 9, 2007 S25FL004A_00_B3 Figure 16.1 SPI Mode 0 (0,0) Input Timing t CSS SU:DAT CRT HD:DAT t CFT MSB IN Figure 16.2 SPI Mode 0 (0,0) Output Timing Figure 16.3 HOLD# Timing ...
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... Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi WPS S25FL004A t WPH S25FL004A_00_B3 July 9, 2007 ...
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... BSC 1.27 BSC L 0.020 0.030 0.508 L1 .055 REF 1.40 REF L2 .010 BSC 0.25 BSC N 8 θ 0˚ 8˚ 0˚ θ1 5˚ 15˚ 5˚ θ2 0˚ July 9, 2007 S25FL004A_00_B3 0. SEE DETAIL E 0.10 C 0.10 C SEATING PLANE ...
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... ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. 3.50 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 8. PIN # TOP WILL BE LASER MARKED. 0.55 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 0. S25FL004A 3448\ 16-038.28 \ 04.15.05 S25FL004A_00_B3 July 9, 2007 ...
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... Added migration text to cover sheet and first page document. Revision B2 (July 2, 2007) Global Added a sentence to Byte or Page Programming. Revision B3 (July 9, 2007) Global Modified migration text to cover sheet and first page document. This product is now retired. July 9, 2007 S25FL004A_00_B3 Description S25FL004A . CC2 ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion Logo, MirrorBit , MirrorBit S25FL004A ® ™ ™ ™ Eclipse , ORNAND , HD-SIM S25FL004A_00_B3 July 9, 2007 ...