S25FL004A Meet Spansion Inc., S25FL004A Datasheet - Page 19

• Manufacturer Part Number: S25FL004A
• Description: 4-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.7
July 9, 2007 S25FL004A_00_B3
Write Status Register (WRSR)
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register,
program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of
these operations is in progress; if WIP is 0, no such operation is in progress.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status
Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0,
the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the
WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program,
or erase operation. WEL cannot be directly set by the WRSR command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against
any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are
non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see
on page
Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected
mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
device ignores any Write Status Register (WRSR) command.
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command.
bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR
commands once it enters the Hardware Protected Mode (HPM).
be driven low and the SRWD bit must be 1 for this to occur.
SCK
CS#
SO
SI
Mode 3
Mode 0
9.7).
Hi-Z
13) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware
0
1
Figure 9.6 Read Status Register (RDSR) Command Sequence
Command
2
D a t a
3
4
Table 9.2, S25FL004A Status Register on page 18
5
S h e e t
6
7
MSB
S25FL004A
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
8
Status Register Out
9
10
11
12
13
14
Table 9.3 on page 20
15
MSB
Status Register Out
shows the status register
shows that W# must
Table 7.1
19