MD51V65160 Oki Semiconductor, MD51V65160 Datasheet - Page 8

• Manufacturer Part Number: MD51V65160
• Description: 4,194,304-word ? 16-bit Dynamic Ram Fast Page Mode Type
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Notes:
10. These parameters are referenced to the UCAS and LCAS, leading edges in an early
11. These parameters are determined by the falling edge of either UCAS or LCAS,
12. These parameters are determined by the rising edge of either UCAS or LCAS,
13. t
14. t
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight
2. The AC characteristics assume t
3. V
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
5. Operation within the t
6. Operation within the t
7. t
8. t
9. t
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
Transition times (t
The output timing reference levels are V
t
t
t
t
circuit condition and are not referenced to output voltage levels.
included in the data sheet as electrical characteristics only. If t
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
t
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
write cycle, and to the WE leading edge in an OE control write cycle, or a read modify
write cycle.
whichever is earlier.
whichever is later.
RCD
RCD
RAD
RAD
OFF
RCH
WCS
AWD
CWL
CP
IH
is determined by the time both UCAS and LCAS are high.
(Min.) and V
, t
(Max.) and t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
(Max.) is specified as a reference point only. If t
or t
(Max.) limit, then the access time is controlled by t
should be satisfied by both UCAS and LCAS.
CWD
t
AWD
RRH
, t
RWD
must be satisfied for a read cycle.
(Min.) and t
, t
OEZ
IL
T
AWD
) are measured between V
(Max.) are reference levels for measuring input timing signals.
(Max.) define the time at which the output achieves the open
RCD
RAD
and t
CPWD
(Max.) limit ensures that t
(Max.) limit ensures that t
CPWD
T
t
= 5 ns.
CPWD
are not restrictive operating parameters. They are
(Min.), then the cycle is a read modify write
OH
CWD
= 2.0 V and V
IH
and V
t
CWD
RCD
RAD
RAC
RAC
IL
CAC
AA
(Min.) , t
.
is greater than the specified
is greater than the specified
(Max.) can be met.
(Max.) can be met.
OL
.
.
= 0.8 V.
WCS
RWD
t
WCS
MD51V65160
t
RWD
(Min.), then
(Min.),
8/16