ad5933 Analog Devices, Inc., ad5933 Datasheet - Page 18

• Manufacturer Part Number: ad5933
• Description: 1 Msps 12-bit Impedance Converter, Network Analyzer
• Manufacturer: Analog Devices, Inc.

AD5933
Block Read
In this operation, the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set. This is again done by setting a pointer to set the
RAM/OTP address.
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the write
bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code (10100001) that tells the
slave device to expect a block read.
5. The slave asserts ACK on SDA.
ERROR CORRECTION
P.E.C.
The AD5933 provides the option of issuing a PEC (Packet Error
Correction) byte after all commands. This enables the user to
verify that the data received by or sent from the AD5933 is
correct. The PEC byte is an optional byte sent after that last data
byte has been written to or read from the AD5933. The protocol
is as follows:
1.
master should check the PEC byte and issue another block read
if the PEC byte is incorrect.
2.
end of the read.
3.
The AD5933 issues a PEC byte to the master. The
A NACK is generated after the PEC byte to signal the
The PEC is generated per the following specifications.
Figure 15. Reading Register Data
SLAVE
ADDRESS
S
SLAVE
ADDRESS
R
A
BYTE0
W A
Figure 16. Performing a block read
BLOCK READ
Rev. PrA | Page 18 of 20
A
BYTE1
6. The master sends a byte count data byte that tells the slave
how many data bytes to expect.
7. The master asserts ACK on SDA.
8 . The master asserts a repeat start condition on SDA. (This is
required to set Read bit high)
9. The master sends the 7-bit slave address followed by the read
bit (high).
10. The slave asserts ACK on SDA.
11. The master receives the data bytes.
12. The master asserts ACK on SDA after each data byte.
14. A NACK is generated after the last byte to signal the end of
the read.
15. The master asserts a STOP condition on SDA to end the
transaction.
Note: The PEC byte is calculated using CRC-8. The Frame
Check Sequence (FCS) conforms to CRC-8 by the polynomial:
CHECKSUM
A checksum register is available to allow the user to verify the
correct contents of the frequency register, frequency increment
register, and number of increments. The checksum register is
based on a error checking algorithm from the above registers.
TBD. The user reads this checksum register and verifies
contents are correct.
USER COMMAND CODES
These command codes are used for reading/writing to the
interface and the memory. They are further explained in the
appropriate sections but are grouped here for ease of reference.
A
NUMBER
BYTES READ
A
BYTE2
Preliminary Technical Data
C
x
A
S
x
S
8

x
2
A

x
P
1

1