ad5933 Analog Devices, Inc., ad5933 Datasheet - Page 8

• Manufacturer Part Number: ad5933
• Description: 1 Msps 12-bit Impedance Converter, Network Analyzer
• Manufacturer: Analog Devices, Inc.

AD5933
SIN ROM
To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Since phase
information maps directly into amplitude, the SIN ROM uses
the digital phase information as an address to a look-up table,
and converts the phase information into amplitude. Although
the NCO contains a 27-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 227 entries. It is necessary only to
have sufficient phase resolution such that the errors due to
truncation are smaller than the resolution of the 10-bitDAC.
This requires the SIN ROM to have two bits of phase resolution
more than the 10-bit DAC. The DDS includes a high impedance
current source 10-bit DAC.
RESPONSE STAGE
The diagram below shows the input stage to pin TF1. Current
from the external sensor load flows through the TF1 pin and
into a transimpedance amplifier which has an external resistor
across its feedback. The user needs to choose a precision
resistor in the feedback loop such that the dynamic range of the
ADC is used. The positive node of the transimpedance
amplifier is biased to VDD/2. The output of the
Transimpedance amplifier can then be gained by either 1 or 5,
and is fed directly into the input of the ADC.
ADC OPERATION
The AD5933 has an integrated on board 12 bit ADC. The ADC
contains an on-chip track and hold amplifier, a successive
approximation A/D converter. Clocking for the A/D is provided
using a divided down ratio of the reference clock.
The A/D is a successive approximation analog to digital
converter, based on a Capacitive DAC design Architecture. The
figures below show simplified schematics of the ADC. The ADC
is comprised of control logic, a SAR, and a capacitive DAC, all
of which are used to add and subtract fixed amounts of charge
from the Sampling capacitor to bring the comparator back into
a balanced condition. The 1st figure shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in position A, the
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on VA1, for example.
VDD/2
TF1
Figure 5.
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ADC
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When the ADC starts a conversion, SW2 will open and SW1
will move to position B, as shown below, causing the
comparator to become unbalanced. The control logic and the
capacitive DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is re-
balanced, the conversion is complete. The control logic
generates the ADC output code.
The start conversion for the ADC is either user controlled via
an external adc_trig pin or can be internally programmed as a
delay from the start of the exitation signal. The data from the
ADC is directly available on the I2C interface or can either be
stored in a FIFO RAM until the entire frequency sweep is
completed.
DFT CONVERSION
A discrete Fourier transform is calculated for each frequency
point in the sweep. The return signal is converted by the ADC,
windowed and then multiplied with a test phasor value to give a
real and imaginary output. This is repeated for 1024 sample
points of the input signal and the results of each multiplication
summed to give a final answer as a complex number. The
resultant answer at each frequency is two 16 bit words, the real
and imaginary data in complex form.
Preliminary Technical Data
Figure 6.
Figure 7.