st52f510 STMicroelectronics, st52f510 Datasheet - Page 21

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

3 ADDRESSING SPACES
ST52F510/F513/F514
addressing spaces:
Each space is addressed by a load type instruction
that indicates the source and the destination space
in the mnemonic code (see Figure 3.1).
3.1 Memory Interface
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriate access time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 3.1 Addressing Spaces
Register File
Program/Data Memory
Stacks
Input Registers
Output Registers
Configuration Registers
PROGRAM/DATA MEMORY
NON VOLATILE MEMORY
LDPE
RAM BANKS
AND STACKS
LDCE
has
LDER
LDRE
six
INPUT REGISTERS
REGISTER FILE
separate
STFive CORE
LDFR
LDRI
LDCNF
GETPG
3.2 Register File
The Register File consists of 256 general purpose
8-bit RAM locations called “registers” in order to
recall the functionality.
The Register File exchanges data with all the other
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
Data can be moved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between
addressing spaces.
3.3 Program/Data Memory
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 256 locations used to
store run-time user data. At least one bench is
present in the devices. RAM benches are also
used to implement both System and User Stacks.
PROCESSOR
REGISTERS
DECISION
PROGRAM
COUNTER
DPU
ALU
CU
PGSETR
the
LDPR
LDCR
Register
CONFIGURATION
ON CHIP PERIPHERALS
REGISTERS
REGISTERS
OUTPUT
ST52F510/F513/F514
File
and
PERIPHERAL
PERIPHERAL
PERIPHERAL
BLOCK
BLOCK
BLOCK
the
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