ltc3850gn-2 Linear Technology Corporation, ltc3850gn-2 Datasheet - Page 22

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ltc3850gn-2

Manufacturer Part Number
ltc3850gn-2
Description
Dual, 2-phase Synchronous Step-down Switching Controller
Manufacturer
Linear Technology Corporation
Datasheet

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Part Number
Manufacturer
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Part Number:
LTC3850GN-2
Manufacturer:
LTNEAR
Quantity:
20 000
LTC3850-2
APPLICATIONS INFORMATION
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
fi lter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specifi ed in the Electrical Characteristics table. Note that the
LTC3850-2 can only be synchronized to an external clock
whose frequency is within range of the LTC3850-2’s internal
V
A simplifi ed block diagram is shown in Figure 11.
22
OSCILLATOR
CO
EXTERNAL
. This is guaranteed to be between 250kHz and 780kHz.
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
Figure 11. Phase-Locked Loop Block Diagram
900
800
700
600
500
400
300
200
100
MODE/
PLLIN
0
0
FREQ/PLLFLTR PIN VOLTAGE (V)
FREQUENCY
0.5
DETECTOR
DIGITAL
PHASE/
1
1.5
2.4V
2
38502 F10
FREQ/
PLLFLTR
2.5
R
LP
38502 F11
VCO
C
LP
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor C
The loop fi lter components, C
current pulses from the phase detector and provide a stable
input to the voltage-controlled oscillator. The fi lter compo-
nents C
lock. Typically R
Typically, the external clock (on MODE/PLLIN pin) input high
threshold is 1.6V, while the input low thres-hold is 1V.
Minimum On-Time Considerations
Minimum on-time t
the LTC3850-2 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3850-2 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
t
ON(MIN)
LP
OSC
and R
<
, current is sunk continuously, pulling down
V
V
IN
OUT
LP
LP
(f)
ON(MIN)
= 10k and C
determine how fast the loop acquires
LP
holds the voltage.
OSC
is the smallest time duration that
, then current is sourced con-
LP
LP
and R
is 2200pF to 0.01μF.
LP
, smooth out the
38502f

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