ltc3850gn-2 Linear Technology Corporation, ltc3850gn-2 Datasheet - Page 24

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ltc3850gn-2

Manufacturer Part Number
ltc3850gn-2
Description
Dual, 2-phase Synchronous Step-down Switching Controller
Manufacturer
Linear Technology Corporation
Datasheet

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LTC3850GN-2
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LTC3850-2
APPLICATIONS INFORMATION
a minimum of 20μF to 40μF of capacitance having a
maximum of 20mΩ to 50mΩ of ESR. The LTC3850-2
2-phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔI
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. The
availability of the I
control loop behavior but also provides a DC coupled and
AC fi ltered closed loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I
in the Typical Application circuit will provide an adequate
starting point for most applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
24
TH
OUT
OUT
series R
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
TH
LOAD
C
OUT
pin not only allows optimization of
fi lter sets the dominant pole-zero
(ESR), where ESR is the effective
. ΔI
TH
LOAD
external components shown
also begins to charge or
OUT
shifts by an
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R
will be increased by decreasing C
the same factor that C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited
to approximately 25 • C
require a 250μs rise time, limiting the charging current
to about 200mA.
LOAD
OUT
to C
, causing a rapid drop in V
OUT
is greater than 1:50, the switch rise time
C
LOAD
is decreased, the zero frequency
C
and the bandwidth of the loop
. Thus a 10μF capacitor would
TH
TH
pin waveforms that will
C
. If R
pin signal which is in
OUT
. No regulator can
C
is increased by
38502f

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