p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 378

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2006 Page 340 of 658
REJ09B0310-0100
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
PER ∨ FER ∨ ORER = 1
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
All data received?
FER flags in SSR
End of reception
Start reception
Initialization
Figure 15.9 Sample Serial Reception Flowchart (1)
RDRF = 1
Yes
Yes
No
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[6]
[3]
[1]
[2]
[4]
[5] Serial reception continuation procedure:
[Legend]
∨ : Logical OR
Note: The SMR, SCR, SCMR, and BRR registers
SCI initialization:
The RxD pin is automatically designated as
the receive data input pin.
[3] Receive error processing and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After performing the appropriate error
processing, ensure that the ORER, PER, and
FER flags are all cleared to 0. Reception
cannot be resumed if any of these flags are
set to 1. In the case of a framing error, a
break can be detected by reading the value
of the input port corresponding to the RxD
pin.
SCI status check and receive data read:
Read SSR and check that RDRF = 1, then
read the receive data in RDR and clear the
RDRF flag to 0. Transition of the RDRF flag
from 0 to 1 can also be identified by an RXI
interrupt.
To continue serial reception, before the stop
bit for the current frame is received, read the
RDRF flag, read RDR, and clear the RDRF
flag to 0.
However, the RDRF flag is cleared
automatically when the DTC is initiated by an
RXI interrupt and reads data from RDR.
should not be written to during the period from
the start to the end of reception. This does not
apply to the processing at step [6].