rm5231 pmc-sierra, rm5231 Datasheet - Page 18

• Manufacturer Part Number: rm5231
• Description: Rm5231 Microprocessor With 32-bit System Bus Released
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002165, Issue 1
3.15 Instruction TLB
3.16 Data TLB
3.17 Cache Memory
3.18 Instruction Cache
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine the following coherency algorithms:
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The non-coherent protocols are used for both code and data on the RM5231, with data using write-
back or write-through depending on the application. The coherency attributes generate coherent
transaction types on the system interface. However, in the RM5231 cache coherency is not
supported, hence the coherency attributes should never be used.
The RM5231 implements a 2-entry instruction TLB (ITLB) to minimize contention for the JTLB,
eliminate the timing critical path of translating through a large associative array, and save power.
Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction
address translation to occur in parallel with data address translation. When a miss occurs on an
instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the
JTLB. The operation of the ITLB is completely transparent to the user.
The RM5231 implements a 4-entry data TLB (DTLB) for the same reasons cited above for the
ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in parallel with instruction address translation. When a miss occurs on
a data address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is
pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The
operation of the DTLB is completely transparent to the user.
In order to keep the RM5231’s high-performance pipeline full and operating efficiently, the
RM5231 incorporates on-chip instruction and data caches that can be accessed in a single
processor cycle. Each cache has its own 64-bit data path and both caches can be accessed
simultaneously. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of over 3 GB per second at an internal clock frequency of 200 MHz.
The RM5231 incorporates a two-way set associative on-chip instruction cache. This virtually
indexed, physically tagged cache is 32 KB in size and is protected with word parity.
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
uncached
non-coherent write-back
non-coherent write-through with write-allocate
non-coherent write-through without write-allocate
sharable
exclusive
update
RM5231™ Microprocessor with 32-bit System Bus Data Sheet
Released
18