rm5231 pmc-sierra, rm5231 Datasheet - Page 9

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rm5231

Manufacturer Part Number
rm5231
Description
Rm5231 Microprocessor With 32-bit System Bus Released
Manufacturer
pmc-sierra
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002165, Issue 1
1
Features
Dual Issue superscalar microprocessor
System interface optimized for embedded applications
Integrated on-chip caches
Integrated memory management unit
High-performance floating-point unit — up to 500 MFLOPS
MIPS IV instruction set
Embedded application enhancements
Fully static 0.25 micron CMOS design with power down logic
128-pin Power-Quad 4 (QFP) package
150, 200, & 250 MHz operating frequencies
300 Dhrystone2.1 MIPS
32-bit system interface lowers total system cost
High-performance write protocols maximize uncached write bandwidth
Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
2.5 V core with 3.3 V IOs
IEEE 1149.1 JTAG boundary scan
32 KB instruction and 32 KB data — 2 way set associative
Per set locking
Virtually indexed, physically tagged
Write-back and write-through on a per page basis
Pipeline restart on first doubleword for data cache misses
Fully associative joint TLB (shared by I and D translations)
48 dual entries map 96 pages
Variable page size (4 KB to 16 MB in 4x increments)
Single cycle repeat rate for common single-precision operations and some double pre-
cision operations
Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
Single cycle repeat rate for single-precision combined multiply-add operation
Floating point multiply-add instruction increases performance in signal processing
and graphics applications
Conditional moves to reduce branch frequency
Index address modes (register + register)
Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
I and D cache locking by set
Optional dedicated exception vector for interrupts
Standby reduced power mode with WAIT instruction
2.5 V core with 3.3 V I/O
RM5231™ Microprocessor with 32-bit System Bus Data Sheet
Released
9

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