s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 24

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

24
7.3.4.1
7.3.4.2
Note
For CR0[14:11], only the settings shown in
Device Read Mode
Configuration Register zero bit 15 (CR0.15) controls whether read accesses via the bus interface are in
asynchronous or synchronous mode. Asynchronous mode is the default after power-on or hardware reset.
Write accesses are always conducted with asynchronous mode timing, independent of the read mode.
Initial Access Cycles
Configuration Register zero bits 14 to 11 (CR0.[14:11]) define the total number of cycles after the AVD# Low
cycle that captures the initial address through the cycle that read data is valid. The bits from 14 to 11 are in
most to least significant order. The random address access at the beginning of each read burst takes longer
than the subsequent read cycles. The memory bus interface must be told how many cycles to wait before
driving valid data then advancing to the next data word. The number of initial cycles will vary with the memory
clock rate. The minimum number of cycles is 3 and the maximum is 14. The default after power-on or
hardware reset is 13 cycles.
SICR BIt
CR0.15
CR0.14
CR0.13
CR0.12
CR0.11
CR0.10
CR0.9
CR0.8
CR0.7
CR0.6
CR0.5
CR0.4
CR0.3
CR0.2
CR0.1
CR0.0
Output Drive Strength
Initial Access Cycles
Device Read Mode
Read Burst Length
Programmable
RDY Polarity
RDY Timing
Function
Reserved
Reserved
Reserved
Reserved
Reserved
S29NS-S MirrorBit
D a t a
Table 7.2
Table 7.4 Configuration Register 0 (CR0)
are tested and supported.
S h e e t
®
(All other bit settings are reserved)
Eclipse
0000 = Reserved
0001 =
0010 =
0011 =
1011 =
1100 =
1101 =
1110 = Reserved
1111 = Reserved
000 = Continuous (Default)
010 = 8 word (16-Byte) Linear Burst with wrap around
011 = 16 word (32-Byte) Linear Burst with wrap around
0 = Synchronous Read Mode
1 = Asynchronous Read Mode (Default)
0 = RDY signal is active low
1 = RDY signal is active high (Default)
0 = Reserved
1 = Reserved (Default)
0 = RDY active one clock cycle before data
1 = RDY active with data (Default)
0 = Full Drive= Current Driver Strength (Default)
1 = Half Drive
0 = Reserved
1 = Reserved (Default)
0 = Reserved (Default)
1 = Reserved
0 = Reserved (Default)
1 = Reserved
0 = Reserved
1 = Reserved (Default)
.
.
.
™
Initial data is valid on the
Flash Family
( P r e l i m i n a r y )
Settings (Binary)
3rd
4th
5th
.
.
.
13th (Default)
14th
15th
S29NS-S_00_02 April 20, 2009
rising CLK edge after
address is latched