sam4s8c ATMEL Corporation, sam4s8c Datasheet - Page 28

• Manufacturer Part Number: sam4s8c
• Description: At91sam Arm-based Flash Mcu
• Manufacturer: ATMEL Corporation

7.5
7.6
28
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
Instance name
Slaves
USART1
USART0
0
1
2
3
4
UART1
UART0
HSMCI
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
DACC
PWM
TWI1
TWI0
SSC
SPI
SAM4S Master to Slave Access
Peripheral DMA Controller
External Bus Interface
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Masters
Cortex-M4 I/D
Bus
X
X
0
-
-
-
Cortex-M4 S
Bus
X
X
X
1
-
-
11100AS–ATARM–27-Oct-11
PDC
X
X
X
2
X
-
CRCCU
X
X
3
X
X
-