ics86953i-147 Integrated Device Technology, ics86953i-147 Datasheet
ics86953i-147
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ics86953i-147 Summary of contents
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... HiPerClockS™ tor. The PCLK, nPCLK pair can accept most standard differential input levels. With output frequencies up to 175MHz, the ICS86953I-147 is targeted for high per- formance clock applications. Along with a fully integrated PLL, the ICS86953I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. ...
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... ICS86953I-147 ABLE IN ESCRIPTIONS ...
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... ICS86953I-147 BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...
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... ICS86953I-147 T 5. PLL ABLE NPUT EFERENCE HARACTERISTICS ABLE HARACTERISTICS DDA ...
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... ICS86953I-147 P ARAMETER 1.65V± DDA V DDO LVCMOS GND -1.65V±5% 3. UTPUT OAD EST IRCUIT V DDO Q0:Q7, 2 QFB ➤ tcycle n tjit(cc) = tcycle n – tcycle n+1 1000 Cycles YCLE TO YCLE ITTER 80% 20% Q0:Q7, t QFB UTPUT ISE ALL IME Q0:Q7, QFB PERIOD ...
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... ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS86953I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V individually connected to the power supply plane through vias, and 0.01µ ...
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... ICS86953I-147 LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other dif- ferential signals. Both differential inputs must meet the V V input requirements. Figures show interface ex- CMR amples for the PCLK/nPCLK input driven by the most common 3 ...
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... ICS86953I-147 L G AYOUT UIDELINE The schematic of the ICS86953I-147 layout example is shown in Figure 4A. The ICS86953I-147 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will depend VCC Ohm Ohm ...
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... The series termination resistors should be located as close to the driver pins as possible VCCA U1 Pin Ohm Trace F 4B. PCB IGURE OARD AYOUT 9 the transmission lines. GND 50 Ohm Trace VDD VIA Other signals ICS86953I-147 OR ©2010 Integrated Device Technology, Inc. ...
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... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS86953I-147 is: 1758 ICS86953BYI-147 REVISION B FEBRUARY 26, 2010 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER R I ELIABILITY ...
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... ICS86953I-147 ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-026 ICS86953BYI-147 REVISION B FEBRUARY 26, 2010 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER LQFP EAD ACKAGE IMENSIONS ...
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... ICS86953I-147 ABLE RDERING NFORMATION ...
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... ICS86953I-147 & ICS86953BYI-147 REVISION B FEBRUARY 26, 2010 ...
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... ICS86953I-147 www.IDT.com 6024 Silver Creek Valley Road Sales San Jose, CA 95138 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice ...