ics86953 Integrated Device Technology, ics86953 Datasheet
ics86953
Related parts for ics86953
ics86953 Summary of contents
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... PCLK, nPCLK pair can accept most standard dif- ferential input levels. With output frequencies up to 110MHz, the ICS86953I is targeted for high performance clock applica- tions. Along with a fully integrated PLL, the ICS86953I contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. ...
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... www.icst.com/products/hiperclocks.html 2 ICS86953I KEW D ERO ELAY ...
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... www.icst.com/products/hiperclocks.html 3 ICS86953I KEW D ERO ELAY = -40°C 85° ...
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... www.icst.com/products/hiperclocks.html 4 ICS86953I KEW D ERO ELAY = -40°C 85° ...
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... UTPUT nPCLK 2V PCLK 0. Q0:Q7, QFB P ROPAGATION nPCLK PCLK 2 FB_CLK (where t (Ø) is any random sample, and t (Ø) of the sampled cycles measured on controlled edges HASE ITTER ERIOD www.icst.com/products/hiperclocks.html 5 ICS86953I KEW D ERO ELAY I NFORMATION V Cross Points NPUT EVEL V DDO 2 V DDO 2 ...
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... T OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS86953I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V and V DDA DDO connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...
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... H N NPUT RIVEN IGURE 3.3V 3.3V R4 125 LVDS CLK nCLK HiPerClockS Input R2 84 PCLK 3D NPUT RIVEN IGURE RIVER www.icst.com/products/hiperclocks.html 7 ICS86953I KEW D ERO ELAY 2.5V 3.3V 2. 120 120 SSTL Ohm PCLK Ohm nPCLK R1 R2 120 120 PCLK/ PCLK I ...
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... Circuit Systems, Inc AYOUT UIDELINE The schematic of the ICS86953I layout example is shown in Figure 4A. The ICS86953I recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will VDD 10u ...
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... The series termination resistors should be located as close to the driver pins as possible. 50 Ohm Trace Ohm Trace 4B. PCB IGURE OARD AYOUT OR www.icst.com/products/hiperclocks.html 9 ICS86953I KEW D ERO ELAY GND VDD VIA Other signals C5 C4 ICS86953I REV. B APRIL 23, 2004 , UFFER ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS86953I is: 1758 86953BYI D - -LVCMOS / LVTTL Z IFFERENTIAL TO ...
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... ° www.icst.com/products/hiperclocks.html 11 ICS86953I KEW D ERO ELAY ...
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... www.icst.com/products/hiperclocks.html 12 ICS86953I KEW D ERO ELAY ° ...
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... www.icst.com/products/hiperclocks.html 13 ICS86953I KEW D ERO ELAY ...