ics86953 Integrated Device Technology, ics86953 Datasheet - Page 9

• Manufacturer Part Number: ics86953
• Description: Lvpecl-input Lvcmos-output 1 9 110-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
C
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
86953BYI
OWER AND
LOCK
T
RACES AND
G
DDA
Integrated
Circuit
Systems, Inc.
ROUNDING
pin as possible.
T
C16
ERMINATION
C11
R7
VCCA
Pin 1
U1
F
IGURE
D
www.icst.com/products/hiperclocks.html
4B. PCB B
IFFERENTIAL
C2
R2
OARD
50 Ohm
Trace
C1
-
9
TO
L
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
AYOUT
-LVCMOS / LVTTL Z
• The differential 50Ω output traces should have same
• Avoid sharp angles on the clock trace. Sharp angle turns
• Keep the clock traces on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
• The series termination resistors should be located as
R1
length.
cause the characteristic impedance to change on
the transmission lines.
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
clock trace pair.
close to the driver pins as possible.
C3
50 Ohm
Trace
F
OR
ICS86953I
C5
C4
ERO
L
Other
signals
GND
OW
VDD
VIA
ICS86953I
D
S
ELAY
KEW
REV. B APRIL 23, 2004
, 1-
B
UFFER
TO
-9