ics86953 Integrated Device Technology, ics86953 Datasheet - Page 6

• Manufacturer Part Number: ics86953
• Description: Lvpecl-input Lvcmos-output 1 9 110-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
P
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS86953I provides separate
power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each V
86953BYI
OWER
IRING THE
S
UPPLY
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
F
ILTERING
DDA
T
I
and V
NPUT TO
ECHNIQUES
Single Ended Clock Input
F
IGURE
DDO
A
should be individually
1. S
A
D
PPLICATION
www.icst.com/products/hiperclocks.html
CCEPT
INGLE
IFFERENTIAL
DDA
C1
0.1u
E
pin.
NDED
S
V_REF
INGLE
DD
/2 is
S
IGNAL
E
-
6
TO
I
NDED
D
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
1K
RIVING
R1
1K
R2
-LVCMOS / LVTTL Z
VDD
L
D
EVELS
nPCLK
IFFERENTIAL
PCLK
F
IGURE
I
NPUT
2. P
V
V
DDO
DDA
OWER
DD
.01µF
= 3.3V, V_REF should be 1.25V
.01µF
S
UPPLY
ERO
L
3.3V
OW
ICS86953I
10Ω
10 µF
F
D
ILTERING
S
ELAY
KEW
REV. B APRIL 23, 2004
, 1-
B
UFFER
TO
-9