ics86953 Integrated Device Technology, ics86953 Datasheet - Page 7

• Manufacturer Part Number: ics86953
• Description: Lvpecl-input Lvcmos-output 1 9 110-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

86953BYI
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
F
F
IGURE
IGURE
CMR
3.3V
3C. H
3A. H
3.3V
input requirements. Figures 3A to 3D show inter-
LVPECL
CML
BY A
BY A
LOCK
I
I
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL D
CML D
C
C
Zo = 50 Ohm
Zo = 50 Ohm
I
LOCK
LOCK
NPUT
S PCLK/
S PCLK/
RIVER
SWING
I
NTERFACE
3.3V
R3
125
3.3V
R1
50
and V
R1
84
R2
50
N
N
RIVER
R4
125
PCLK I
PCLK I
R2
84
OH
PCLK
nPCLK
must meet the V
3.3V
D
CLK
nCLK
www.icst.com/products/hiperclocks.html
3.3V
HiPerClockS
PCLK/nPCLK
IFFERENTIAL
NPUT
NPUT
HiPerClockS
Input
D
D
RIVEN
RIVEN
PP
-
7
TO
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
F
IGURE
IGURE
-LVCMOS / LVTTL Z
3.3V
3D. H
3B. H
LVDS
2.5V
SSTL
BY A
BY AN
Zo = 50 Ohm
Zo = 50 Ohm
I
I
P
P
ER
ER
3.3V LVDS D
C
Zo = 60 Ohm
Zo = 60 Ohm
C
SSTL D
LOCK
LOCK
R5
100
S PCLK/
S PCLK/
RIVER
2.5V
R3
120
R1
120
C1
C2
RIVER
ERO
L
R4
120
OW
N
R2
120
N
3.3V
R3
1K
PCLK I
PCLK I
ICS86953I
R1
1K
D
S
PCLK
nPCLK
R4
1K
ELAY
3.3V
R2
1K
KEW
REV. B APRIL 23, 2004
PCLK
nPCLK
NPUT
NPUT
HiPerClockS
PCLK/nPCLK
3.3V
, 1-
B
HiPerClockS
PCL K/n PC LK
D
D
UFFER
RIVEN
RIVEN
TO
-9