cat24c164 Catalyst Semiconductor, cat24c164 Datasheet - Page 4

• Manufacturer Part Number: cat24c164
• Description: 16-kb Cmos Serial Eeprom, Cascadable
• Manufacturer: Catalyst Semiconductor

POWER-ON RESET (POR)
CAT24C164 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24C164 device will power up into Standby mode
after V
down into Reset mode when V
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
The CAT24C164 can be made compatible with the
CAT24C16 by tying A2, A1 and A0 to V
A2, A1 and A0 float.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C164 supports the Inter-Integrated Circuit
(I
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C164
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver.
Doc. No. 1118, Rev. A
CAT24C164
2
C) Bus data transmission protocol, which defines a
CC
exceeds the POR trigger level and will power
CC
drops below the POR
SS
or by leaving
4
I
The I
two wires are connected to the V
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular Slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Figure 2). The next three significant bits (A2, A1, A0)
are the device address bits and define which device or
which part of the device the Master is accessing (The
A1 bit must be the compliment of the A1 input pin signal).
Up to eight CAT24C164 devices may be individually ad-
dressed by the system. The next three bits are used as
the three most significant bits of the data word address.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
2
C BUS PROTOCOL
th
2
C bus consists of two ‘wires’, SCL and SDA. The
clock cycle. As long as the Master acknowledges
th
clock cycle (Figure 3). The Slave will
Characteristics subject to change without notice
© 2006 by Catalyst Semiconductor, Inc.
CC
supply via pull-up