mpc93h51 Integrated Device Technology, mpc93h51 Datasheet - Page 6

• Manufacturer Part Number: mpc93h51
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93H51
Low Voltage PLL Clock Driver
6
Programming the MPC93H51
into several divider modes. In addition, the external feedback
of the device allows for flexibility in establishing various input-
to-output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
Table 7
table describes the outputs using the input clock frequency
CLK as a reference.
Table 7. Output Frequency Relationship
Using the MPC93H51 in Zero-Delay Applications
MPC93H51. For these applications the MPC93H51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale Semiconductor
MC100EP111 or MC10EP222, taking advantage of its
superior low-skew performance. Clock trees using LVPECL
for clock distribution and the MPC93H51 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers.
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
MPC93H51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t
(t
MPC93H51
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
JIT(∅)
The MPC93H51 clock driver outputs can be configured
Nested clock trees are typical applications for the
The external feedback option of the MPC93H51 PLL
The remaining insertion delay (skew error) of the
FSELA
, phase or long-term jitter), feedback path delay and
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
illustrates the various output configurations. The
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(1)
(∅)
APPLICATIONS INFORMATION
for an Example Configuration
), I/O jitter
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
240 MHz while the VCO frequency range is specified from
200 MHz to 480 MHz and should not be exceeded for stable
operation.
the output-to-output skew (t
output.
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
fref = 100 MHz
The output division settings establish the output
CLK
CLK
CLK
CLK
QA
Figure 3. MPC93H51 Zero-Delay Configuration
1
1
1
0
0
0
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
2 * CLK
TCLK
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QB
100 MHz (Feedback)
(Feedback of QD4)
Advanced Clock Drivers Device Data
Outputs
MPC93H51
SK(O)
relative to the feedback
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Freescale Semiconductor
QC
QC0
QC1
QD0
QD1
QD2
QD3
QD4
QA
QB
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
2 x 100 MHz
2 x 100 MHz
4 x 100 MHz
2* CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QD
NETCOM
MPC93H51